riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,502 Commits 1 Branch 0 Tags 13 MiB
4ab1585a78
Commit Graph

5502 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andrew Waterman
80d826b94a Make DTIM deduplicatable 2017-04-26 19:35:35 -07:00
Andrew Waterman
418879a47f Add Instruction Tightly Integrated Memory 2017-04-26 19:35:35 -07:00
Andrew Waterman
ee6702e5e0 Support indexing 1-entry Seqs 
It's a zero-width wire special case.

Closes #706.
 2017-04-26 19:35:35 -07:00
Andrew Waterman
2e23d46631 Use val instead of def in ECC calculations 
This allows nicer-looking code to avoid generating lots of redundant nodes.
 2017-04-26 19:35:35 -07:00
Henry Cook
635f119422 Merge pull request #709 from ucb-bar/bump-hardfloat 
bump hardfloat
 2017-04-26 16:47:49 -07:00
Henry Cook
ebe27614d2 bump hardfloat 2017-04-26 15:37:29 -07:00
Henry Cook
0a9f632cb0 Merge pull request #708 from ucb-bar/debug_busy_data 
debug: Prevent writes to DATA/PROGBUF when busy
 2017-04-26 14:32:10 -07:00
Megan Wachs
7ad4cc36f7 debug: Prevent writes to DATA/PROGBUF when busy 2017-04-26 11:11:21 -07:00
Megan Wachs
e9db531e81 point to riscv-tools README for dependencies (#705) 
As pointed out, if we just point to 'master' branch, then people wouldn't get the correct list of dependencies.
 2017-04-25 20:20:27 -07:00
Henry Cook
1bdb247002 Merge pull request #697 from ucb-bar/async_queue_option 
Add narrowData option to AsyncQueue.
 2017-04-25 17:43:28 -07:00
Henry Cook
7f5f1c7631 Merge branch 'master' into async_queue_option 2017-04-25 14:58:11 -07:00
Henry Cook
95591cc608 Merge pull request #704 from ucb-bar/verbose-require 
Miscellaneous uncore cleanups
 2017-04-25 14:57:58 -07:00
Henry Cook
9bb0d92381 Merge branch 'master' into async_queue_option 2017-04-25 11:23:22 -07:00
Henry Cook
60d71efa36 ahb: make hreadyout fuzzing a sram parameter 2017-04-25 11:11:31 -07:00
Henry Cook
ca435c2f40 uncore: more verbose requires 2017-04-25 11:11:31 -07:00
Wesley W. Terpstra
f3ab23d068 dcache: fix stupidly wrong crossing comparison (#703) 2017-04-25 09:18:41 -07:00
Wesley W. Terpstra
4807ce7ced dcache: put a flow Q to absorb back-pressure without restarting pipeline (#701) 
* dcache: put a flow Q to absorb back-pressure without restarting pipeline

When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.

* dcache: provision as few stages as possible
 2017-04-24 23:28:04 -07:00
Wesley W. Terpstra
9c1d126965 Allow speculative fetch to uncacheable memory if it hits in I$ (#700) 
@aswaterman it's in
 2017-04-24 19:12:37 -07:00
Wesley W. Terpstra
11ff4dfbb9 rocket: seip (int 9) is only present if VM is enabled (#699) 2017-04-24 15:58:33 -07:00
Wesley W. Terpstra
d0f3004097 tilelink2: help tools save some registers in the WidthWidget (#691) 2017-04-24 15:13:58 -07:00
Andrew Waterman
65928dc6a0 Don't push RAS for "auipc ra, X; jalr ra, ra, Y" 2017-04-24 02:01:15 -07:00
Andrew Waterman
36a7971975 Bypass scoreboard to reduce MMIO latency 2017-04-24 02:01:15 -07:00
Andrew Waterman
845e6f7458 Filter out duplicate test suites 
I botched the refactoring in 5934c7b4b9
 2017-04-24 02:01:15 -07:00
Andrew Waterman
f2d4cb8152 Update RAS speculatively from fetch stage 2017-04-24 02:01:15 -07:00
Andrew Waterman
3b2c15b648 Use tininess-after-rounding in FPU 2017-04-24 02:01:15 -07:00
Andrew Waterman
c36c171202 Use correct interrupt priority order 2017-04-24 02:01:15 -07:00
Andrew Waterman
bf861293d9 Add ShiftQueue; use it 2017-04-24 02:01:15 -07:00
Andrew Waterman
d24d8ff84b Don't stall the frontend, making it easier to add more features later 2017-04-24 02:01:15 -07:00
Andrew Waterman
061a0adceb Fetch smaller parcels from the I$ 2017-04-24 02:01:15 -07:00
Ben Keller
0aa8f7d61d Add narrowData option to AsyncQueue. 
This option reduces the number of wires that cross the clock boundary.
This can be a useful feature if the clock boundary coincides with
a voltage boundary, in which case the number of level shifters is reduced.
However, this introduces a path that crosses from sink->source->sink domain,
so the option is disabled by default.
 2017-04-21 16:31:17 -07:00
Megan Wachs
c72b15f2a0 Down with any require() statement that makes me RTFC 2017-04-21 15:44:42 -07:00
Andrew Waterman
458d80cb18 For Verilator, rename +start to +dump-start to match VCS 2017-04-20 17:00:46 -07:00
Andrew Waterman
2faf8ea239 Add +dump-start=N option to VCS 
Starts dumping waveform on cycle N.

Can control stop cycle with +max-cycles.
 2017-04-20 17:00:46 -07:00
Henry Cook
54820e094d Make more require statements in diplomacy verbose (#693) 
* diplomacy: add more verbose requirements
* bump firrtl
 2017-04-20 13:18:39 -07:00
Henry Cook
ef8a819763 Miscellaneous periphery improvements (#689) 
* fifofixer: work around zero-width wires for single source id
* periphery: sourceshrinker takes maxInFlight parameter
 2017-04-20 11:28:00 -07:00
Megan Wachs
9002e7e532 debug: Debug Module needs to handle DMI NOPs even if DTM won't send them. 2017-04-20 10:19:50 -07:00
Megan Wachs
cc7f0a5b7a debug: whitespace cleanup 2017-04-20 10:19:50 -07:00
Megan Wachs
5934779082 debug: Clean up ValidReg assertion. 2017-04-20 10:19:50 -07:00
Megan Wachs
0c013a56c0 debug: Make DMI NOPs really NOPs. 
This simplifies SW design and CDC issues.
 2017-04-20 10:19:50 -07:00
Andrew Waterman
67404a665b When not using a cache, LR/SC isn't legal even on cacheable memory 2017-04-20 08:47:03 -07:00
Megan Wachs
1be13d6b4c PLIC: To avoid hazard between enable -> claim, enforce concurrency=1 2017-04-19 21:37:37 -07:00
Megan Wachs
3dfd584075 regmapper: remove the Pipe in the RegMapper Queue 
With this pipe here, devices which declare concurrency > 0
actually accept transactions on the same cycle they complete
the previous one. This is unexpected behavior.
 2017-04-19 21:37:37 -07:00
Wesley W. Terpstra
b4d17c76d1 coreplex: make rational+synchronous crossing configurable (#688) 2017-04-19 16:16:05 -07:00
Megan Wachs
408107447c debug: DMI response should be busy, not zero, when there is an error. (#685) 2017-04-18 21:41:52 -07:00
Andrew Waterman
d82a0dc231 Mitigate D$ exception critical path, yet again 2017-04-18 00:47:58 -07:00
Andrew Waterman
c99ce7ce5d Only report D$ exceptions on not-nacked accesses 2017-04-18 00:47:58 -07:00
Andrew Waterman
5934c7b4b9 Fix description of LR/SC test suites 2017-04-18 00:47:58 -07:00
Andrew Waterman
a956b78dd2 In TLBPermissions, merge across some region types 
We only care whether they have side effects or not.
 2017-04-18 00:47:58 -07:00
Andrew Waterman
6de6f38894 Pipeline D$ exception response into s2 2017-04-18 00:47:58 -07:00
Andrew Waterman
657f4d4e0c Permit early grant acks to broadcast hub 2017-04-18 00:47:58 -07:00