Andrew Waterman
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410e9cf736
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I$ bugfix, to be reworked
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2017-03-31 12:17:41 -07:00 |
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Henry Cook
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9f371abf3b
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Merge pull request #638 from ucb-bar/riscv-tools-on-priv-1.10
Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v0…
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2017-03-31 01:56:36 -07:00 |
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Henry Cook
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e92eaa7156
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Merge branch 'master' into riscv-tools-on-priv-1.10
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2017-03-30 22:31:29 -07:00 |
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Henry Cook
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e8f337e963
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Merge pull request #636 from ucb-bar/name-rams
Name L1$ RAMs consistently
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2017-03-30 22:30:12 -07:00 |
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Megan Wachs
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dec567ab0c
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Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v013 version.
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2017-03-30 20:22:54 -07:00 |
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Henry Cook
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b9550e8523
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Merge branch 'master' into name-rams
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2017-03-30 17:36:01 -07:00 |
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Henry Cook
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b6da81a66c
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Merge pull request #624 from ucb-bar/debug_v013_pr
Debug v013 [WIP]
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2017-03-30 17:35:26 -07:00 |
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Andrew Waterman
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a8a2ee711c
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Give I$ RAMs consistent names
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2017-03-30 15:50:54 -07:00 |
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Andrew Waterman
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2720095b8e
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Give D$ RAMs consistent names
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2017-03-30 15:49:14 -07:00 |
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Andrew Waterman
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70e7e90c02
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Remove splitMetadata option from L1 caches
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
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2017-03-30 15:48:55 -07:00 |
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Henry Cook
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bcaee9834c
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travis_wait 30
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2017-03-30 13:22:33 -07:00 |
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Megan Wachs
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0828ebe911
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debug_v013: bump fesvr to use autoexec feature for memory writes.
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2017-03-30 11:46:28 -07:00 |
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Megan Wachs
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9de06f8c83
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Merge remote-tracking branch 'origin/master' into debug_v013_pr
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2017-03-30 08:01:11 -07:00 |
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Schuyler Eldridge
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c61714a465
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Pass MODEL variable to emulator.cc
This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.
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2017-03-30 02:08:01 -07:00 |
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Andrew Waterman
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fd39eadcd6
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New PMP encoding
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2017-03-30 00:36:23 -07:00 |
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Wesley W. Terpstra
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2f2b472098
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rocket: split the interrupt controller into its own node
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2017-03-30 00:36:23 -07:00 |
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Wesley W. Terpstra
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a2fc51d65e
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soc: compatible with "simple-bus" => scanned for platform devices
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2017-03-30 00:36:23 -07:00 |
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Alex Solomatnikov
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9f85b2e996
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Do allow make to remove .vpd files on Ctrl-C
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2017-03-30 00:36:23 -07:00 |
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Andrew Waterman
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3546c8d133
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If any PMPs are supported, all CSRs exist
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2017-03-30 00:36:23 -07:00 |
|
Andrew Waterman
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8f73a58d90
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Report access exception, not page fault, if page-table walk fails
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2017-03-30 00:36:23 -07:00 |
|
Andrew Waterman
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25232070ec
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Don't redundantly set resp_ae in PTW
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2017-03-30 00:36:23 -07:00 |
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Andrew Waterman
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80fb002962
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Don't use Vec as lvalue
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2017-03-30 00:36:23 -07:00 |
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Henry Cook
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d3bc99e253
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get local interrupts out of the tile
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2017-03-30 00:36:23 -07:00 |
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solomatnikov
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0b9fc94421
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Assertion for back-to-back uncached and cached ops (#631)
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2017-03-29 23:07:17 -07:00 |
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Megan Wachs
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a14b7b5794
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debug_v013: bump riscv-tools for slightly more efficient FESVR
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2017-03-29 21:42:36 -07:00 |
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Megan Wachs
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24509fc69f
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debug_v013: Bump FESVR to pick up minor off-by-1 in error printing code.
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2017-03-29 15:20:07 -07:00 |
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Megan Wachs
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d8033b20fc
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Merge remote-tracking branch 'origin/master' into debug_v013_pr
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2017-03-29 14:58:04 -07:00 |
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Megan Wachs
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f6e72a3ef6
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debug: Bump riscv-tools to pick up FESVR to version that works with debug v013
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2017-03-29 14:46:06 -07:00 |
|
Megan Wachs
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375a039279
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debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec)
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2017-03-28 21:14:22 -07:00 |
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Megan Wachs
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ca9a5a1cf7
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debug: Fixes in how the SimDTM was hooked up to FESVR
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2017-03-28 21:13:45 -07:00 |
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Megan Wachs
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ff38ebdf5e
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debug: Bump FESVR version to initial Debug v13. Doesn't work yet.
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2017-03-28 21:12:57 -07:00 |
|
Andrew Waterman
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8dfbf4532a
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Use 1 MHz as default timebase (#628)
Defaulting to 0 prevents Linux from booting
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2017-03-28 19:59:56 -07:00 |
|
Andrew Waterman
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44fb3be7d0
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Fix MMIO/cache refill concurrency bug in DCache
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
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2017-03-28 17:16:29 -07:00 |
|
Andrew Waterman
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db3ed12ce3
|
Fix regression in groundtest DummyPTW
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
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2017-03-28 00:56:14 -07:00 |
|
Andrew Waterman
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4215f480ef
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Write instruction to badaddr on illegal instruction traps
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2017-03-28 00:56:14 -07:00 |
|
Megan Wachs
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d6ab929c41
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debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
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2017-03-27 21:25:37 -07:00 |
|
Megan Wachs
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cbc8d2400a
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debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version
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2017-03-27 21:24:44 -07:00 |
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Megan Wachs
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bb64c92906
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csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
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2017-03-27 21:21:48 -07:00 |
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Megan Wachs
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42ca597478
|
debug: Breaking change until FESVR is updated as well.
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
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2017-03-27 21:19:08 -07:00 |
|
Megan Wachs
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43804726ac
|
tilelink2: more helpful requirement message
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2017-03-27 21:05:05 -07:00 |
|
Megan Wachs
|
0c3d85b52b
|
debug: add generated ROM contents and register fields.
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2017-03-27 21:01:36 -07:00 |
|
Megan Wachs
|
877e1cfba1
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debug: add scripts to generate v13 Debug ROM contents.
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2017-03-27 20:51:54 -07:00 |
|
Wesley W. Terpstra
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ed38787c36
|
Merge pull request #622 from ucb-bar/priv-1.10
Various priv-1.10 changes
|
2017-03-27 19:28:30 -07:00 |
|
Andrew Waterman
|
05cbdced78
|
Work around zero-entry vec issue in Chisel
|
2017-03-27 17:57:26 -07:00 |
|
Megan Wachs
|
ab300f7985
|
Update README_TRAVIS.md
|
2017-03-27 17:45:50 -07:00 |
|
Megan Wachs
|
3fc74f3d08
|
Create README_TRAVIS.md
|
2017-03-27 17:45:46 -07:00 |
|
Andrew Waterman
|
d42d8aaea7
|
Make SEIP writable
|
2017-03-27 16:37:09 -07:00 |
|
Andrew Waterman
|
c7c357e716
|
Add local interrupts to core (but not yet to coreplex)
|
2017-03-27 16:37:09 -07:00 |
|
Andrew Waterman
|
069858a20c
|
rocket: separate page faults from physical memory access exceptions
|
2017-03-27 16:37:09 -07:00 |
|
Andrew Waterman
|
ea0714bfcb
|
rocket: hard-wire UXL/SXL fields to 0
a2a3346e73
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2017-03-27 16:37:09 -07:00 |
|