riscv/rocket-chip
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1141 Commits

Author SHA1 Message Date
Wesley W. Terpstra
422e6357a4 tilelink2 RegisterCrossing: Queues go from RV to Irrevocable 
AsyncQueue is still a Queue.
 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
02f89fb530 RegMapper: clarify interface is DecoupledIO 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
8a268268ad tilelink2 RegField: clarify restrictions on functions 
RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
bff0ffa428 tilelink2 RegisterRouter: fix output data glitches 
If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
 2016-10-02 02:24:02 -07:00
Andrew Waterman
e0188f8aa4 Don't implicitly fence on CSR instructions 
CSRs that have an effect on I/O should use an explicit FENCE.
 2016-10-01 19:44:10 -07:00
Andrew Waterman
b772edcb1b Allow hit-under-MMIO and multiple MMIOs in blocking D$ 
The latter feature is by default disabled, since there aren't enough
ID bits.
 2016-10-01 19:44:05 -07:00
Megan Wachs
28eba9b5ac clint/plic: Move the default addresses 2016-10-01 15:46:55 -07:00
mwachs5
9a381e88d1 Suggest sane names for common objects (#369) 
* Suggest sane names for common objects frequently instantiated with factory methods

* Suggest names for common primitives using more Scala-esque Options
 2016-09-30 16:19:25 -07:00
Wesley W. Terpstra
0ebab0976a tilelink2 Isolation: add enable signal (#368) 2016-09-30 04:54:40 -07:00
Wesley W. Terpstra
d3547a6193 tilelink2: Isolation gate insertion module 2016-09-30 01:50:33 -07:00
Wesley W. Terpstra
9b0654be52 tilelink2 Crossing: helpful constructor objects 2016-09-30 01:48:47 -07:00
Wesley W. Terpstra
80f7bb49e3 tilelink2: helper objects operate on OutwardNodes 2016-09-30 01:39:35 -07:00
Howard Mao
4b86802b1a change the configuration interface of SlowIO 2016-09-29 22:16:53 -07:00
Wesley W. Terpstra
6d8c965f04 tilelink2 Crossing: cut the crossing between clock domains 2016-09-29 17:35:10 -07:00
Wesley W. Terpstra
20f42a8762 tilelink2: reuse the halves of the AsyncQueue 2016-09-29 17:35:08 -07:00
Wesley W. Terpstra
8e4c1e567c tilelink2: add types for a TL clockless interface 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
02ce8c2ca4 tilelink2 Nodes: rename RootNode => BaseNode 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
754fcf9831 tilelink2: rename BaseNode to SimpleNode 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
cfdb8ca797 tilelink2 LazyModule: remove obsolete connect method 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
f2e438833c tilelink2 Nodes: generalize a node into inner and outer halves 
This lets us create nodes which transform from one bus to another.
 2016-09-29 17:33:11 -07:00
Andrew Waterman
2bdf8c2be7 Merge branch 'master' into move-to-util 2016-09-29 14:42:11 -07:00
Howard Mao
ab3219cf6e don't use Scala to Chisel implicit conversions outside of rocket 2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67 Move a bunch more things into util package 
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
 2016-09-29 14:23:42 -07:00
Andrew Waterman
e928b741ce Default mtvec=0, not None 
Setting it to None was a mistake.  It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.
 2016-09-29 13:52:41 -07:00
Megan Wachs
45bd63fcc6 jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec 2016-09-29 13:49:14 -07:00
Megan Wachs
449d689a4e jtag: Connect the JTAG DTM side of the synchronizer! 2016-09-29 13:48:55 -07:00
Yunsup Lee
0924f8adb0 print out assigned inerrupt ranges 2016-09-29 11:59:32 -07:00
Yunsup Lee
4c3e8ec1b4 assign interrupt ranges deterministically 2016-09-29 11:59:32 -07:00
Henry Cook
7bca99a27a [tilelink2] Add unit test configs to regression 2016-09-28 18:02:04 -07:00
Henry Cook
32f3f94882 [tilelink2] Fix zero-width wires in RAMModel. 2016-09-28 18:02:04 -07:00
Henry Cook
69e121260e [tilelink2] Add unit tests for many TL2 components 
These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
 2016-09-28 18:02:04 -07:00
Henry Cook
81123f84c9 [tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. (#356) 2016-09-27 18:06:21 -07:00
Howard Mao
c45cc76cef Get rid of remaining MemIO code 
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
 2016-09-27 16:28:17 -07:00
Howard Mao
18e7ea89f2 Get rid of broken groundtests 
The NastiConverterTest, PCIeMockupTest, and DirectGroundtest
configurations have been broken by recent changes.

The NastiConverterTest has been superseded by a unit test and the
other two were only created for an attempt at FPGA debugging.
They weren't actually very useful for that purpose, so might as well get
rid of them.
 2016-09-27 16:28:17 -07:00
Howard Mao
c77c244016 Get rid of NASTI memory interconnects 
These were made for a previous Hurricane tapeout, but we are now doing
all of the memory routing in TileLink, so they are no longer needed.
 2016-09-27 16:28:17 -07:00
mwachs5
f9e0a7ac24 Merge branch 'master' into async_register_crossing 2016-09-27 15:54:34 -07:00
Wesley W. Terpstra
3926cb936b rocketchip: add pbus width and AMO With classes (#357) 2016-09-27 15:52:13 -07:00
Wesley W. Terpstra
eaea138d0d tilelink2: don't use chisel3 namespace (#355) 2016-09-27 14:44:26 -07:00
Henry Cook
f5502df6ab Merge branch 'master' into async_register_crossing 2016-09-27 14:08:27 -07:00
Wesley W. Terpstra
357d06ac9c tilelink2 WidthWidget: Gets must have their mask adjusted (#353) 
The mask of a Get should also be converted.

This manifested as a bug when going from 32=>64 bits. A large Get
could end up with mask that was not full.
 2016-09-27 14:06:02 -07:00
Megan Wachs
3ce08f40a5 crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations 2016-09-27 13:36:28 -07:00
Howard Mao
71a9c78e4b add WidthAdapter from AXI slave to Coreplex TL slave 2016-09-27 12:48:01 -07:00
Howard Mao
7d6fb950b6 Give TileLink IDs more sensible names 
* Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams
 2016-09-27 12:48:01 -07:00
Howard Mao
8a55521b01 move memory width adapter from coreplex to periphery 2016-09-27 12:48:01 -07:00
Howard Mao
e36441a046 use correct parameters object for MMIO width adapter 2016-09-27 12:48:01 -07:00
Howard Mao
201e247f73 Factor coreplex IO connection into separate trait (#350) 
This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.

The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
 2016-09-27 11:55:32 -07:00
Howard Mao
6316ebd58f make naming of L2toMC parameter object consistent between coreplex and periphery 2016-09-26 17:28:21 -07:00
Howard Mao
ea9f0a868f TileLink utility objects should not take implicit parameters 
We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
 2016-09-26 17:28:21 -07:00
Howard Mao
803739a95c Make sure coreplex mmio's TLId is correct (thanks to zizztux) 2016-09-26 17:28:21 -07:00
Howard Mao
c741ada619 get TraceGen working again 2016-09-26 17:28:21 -07:00