Howard Mao
405294167f
fix TL -> Nasti converter w id
2016-08-09 18:24:23 -07:00
Andrew Waterman
2906c75167
Remove fsim, as it is the same as vsim, modulo CONFIG
2016-08-09 15:42:22 -07:00
Andrew Waterman
1b8f919db2
Remove unused CoreName parameter
2016-08-09 15:24:59 -07:00
Andrew Waterman
458520c8f6
Use a generic UInt for TileLink op sizes, rather than MT_xx enum
2016-08-09 15:24:51 -07:00
Andrew Waterman
a857b08c59
[rocket] compute D$ tag bits based upon # of arbiter ports
2016-08-09 14:40:48 -07:00
Howard Mao
2a5aeeae24
add sbt pack plugin ( #197 )
2016-08-08 19:31:03 -07:00
Howard Mao
dd1fed41b6
generate BootROM contents from assembly code
2016-08-05 16:39:21 -07:00
Palmer Dabbelt
dab96096b4
Add firrtl build dependencies
...
Without this when I update firrtl the new version doesn't get built, so
my build is constantly failing.
2016-08-05 14:45:00 -07:00
Howard Mao
9fa5b228b2
allow extra devices and top-level ports to be added without changing RocketChip.scala
2016-08-04 14:06:14 -07:00
Howard Mao
9c4e57aea5
example Rocc accelerator fixes
2016-08-04 11:17:13 -07:00
Howard Mao
410e3e5366
make sure TraceGen gets correct addresses
2016-08-04 11:08:25 -07:00
Howard Mao
0a85e92652
Allow additional internal MMIO devices to be created without changing BaseConfig
2016-08-04 11:04:52 -07:00
Andrew Waterman
cc0f8962fb
[rocket] take physical memory attribute check off critical path
...
Cache the attributes in the TLB instead.
2016-08-02 17:21:03 -07:00
Andrew Waterman
76f33d88a6
[rocket] Respect physical memory protection during page table walks
2016-08-02 17:20:49 -07:00
Andrew Waterman
5d4f6383f2
[rocket] Automatically kill D$ access on address exceptions
...
Doing this internally to the cache eliminates a long control path
from the cache to the core and back to the cache.
2016-08-02 17:20:49 -07:00
Andrew Waterman
b54db0ba23
[rocket] don't update BTB on not-taken branches
...
Only update the BHT; don't set the target prediction to pc+4.
2016-08-02 17:20:49 -07:00
Andrew Waterman
64bde1060c
[rocket] remove unused code in ibuf
2016-08-02 15:26:09 -07:00
Andrew Waterman
2ce702dc0a
[rocket] fix PTW critical path
...
Pipeline the killing of a D$ request following a PTW cache hit.
2016-08-02 15:19:48 -07:00
Andrew Waterman
7e9d139e49
[rocket] remove rocket-specific require() from HasCoreParameters
2016-08-02 15:19:48 -07:00
Andrew Waterman
791a27748b
Update firrtl and remove firrtl hack in plic
2016-08-02 15:19:48 -07:00
Howard Mao
f04aefc95c
get rid of deprecated ZynqAdapter
2016-08-02 13:14:20 -07:00
Howard Mao
63b814fcd7
only run the important (high coverage) tests in regression suite
2016-08-02 10:54:05 -07:00
Howard Mao
b7723f1ff8
make unit tests local to the packages being tested
2016-08-01 17:02:00 -07:00
Howard Mao
98eede0505
some refactoring in RocketChip top-level
2016-08-01 17:02:00 -07:00
Megan Wachs
55c992bb3a
Use FoldRight() instead of for loop
2016-08-01 16:56:33 -07:00
Megan Wachs
8db2e8829f
Allow aggregate CONFIG on Command Line
2016-08-01 14:24:16 -07:00
Andrew Waterman
fe670e5421
Stop using deprecated FileSystemUtilities to create files
2016-07-31 18:04:56 -07:00
Andrew Waterman
832e56d3c7
Fix toBits/toUInt/toSInt deprecation warnings
2016-07-31 17:13:52 -07:00
Andrew Waterman
a6e009d8de
[rocket] Fix frontend mask when fetchWidth == 1
2016-07-31 15:21:17 -07:00
Andrew Waterman
c49dad2e9d
Improve PTW QoR
2016-07-29 17:56:42 -07:00
Andrew Waterman
cc635c386f
Make Chisel3 the default version for SBT
2016-07-29 17:56:42 -07:00
mwachs5
4465260469
Update README.md
...
- List things that are no longer submodules as subpackages instead
- clean up some formatting issues
2016-07-29 17:56:42 -07:00
Andrew Waterman
058396aefe
[rocket] Implement RVC
2016-07-29 17:56:42 -07:00
Andrew Waterman
c465120610
[rocket] use more standard pattern for computing integer min
2016-07-29 17:56:42 -07:00
Andrew Waterman
ffac86b041
[rocket] only write badaddr on certain exceptions
2016-07-29 17:56:42 -07:00
Andrew Waterman
0d3d9fca25
[rocket] Allow zapping of BTB entries
...
This is necessary to guarantee forward progress with RVC, since if the
BTB keeps mispredicting, the processor might never successfully
fetch both halves of a misaligned instruction.
2016-07-29 17:56:42 -07:00
Andrew Waterman
8e0392f24b
[rocket] don't hard-code instruction width in BHT
2016-07-29 17:56:42 -07:00
Howard Mao
f34b0b0447
make sure L2 tracker doesn't read data array again if data buffer already filled
2016-07-29 16:47:31 -07:00
Howard Mao
2891eb879a
add MergedPutRegression to uncover merged put after release bug in L2
2016-07-29 16:42:28 -07:00
Howard Mao
064020bdd7
make sure Memtest generators write different data to each address
2016-07-29 14:22:46 -07:00
Howard Mao
5a3beca097
add RepeatedGetRegression to uncover L2 merged get miss bug
2016-07-28 19:58:47 -07:00
Howard Mao
cb86aaa46b
fix trace generator addresses
2016-07-28 17:56:14 -07:00
Andrew Waterman
8a7fc75b53
fix metadata race in blocking L1 DCache
2016-07-28 17:54:28 -07:00
Howard Mao
bd5972503f
move groundtest/scripts to top-level scripts/
2016-07-28 11:36:55 -07:00
Howard Mao
478f494626
Merge remote-tracking branch 'groundtest/master' into mono-repo
2016-07-28 11:28:06 -07:00
Howard Mao
a5b88d0bdc
Merge remote-tracking branch 'junctions/master' into mono-repo
2016-07-28 11:27:47 -07:00
Howard Mao
373fd427dc
Merge remote-tracking branch 'rocket/master' into mono-repo
2016-07-28 11:27:29 -07:00
Howard Mao
ce242b8f3f
Merge remote-tracking branch 'uncore/master' into mono-repo
2016-07-28 11:23:31 -07:00
Howard Mao
aefba04fb3
get rid of submodules in preparation for merging
2016-07-28 11:21:08 -07:00
Howard Mao
6de2a3e3b1
get rid of fpga-zynq submodule
2016-07-28 11:07:47 -07:00
