Andrew Waterman
c8338ad809
Instantiate Debug Module ( #119 )
2016-06-02 10:53:41 -07:00
Howard Mao
f52fc655a5
remove zscale
2016-05-19 09:43:15 -07:00
Palmer Dabbelt
cddfdf0929
Add CHISEL_VERSION make argument
...
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
Palmer Dabbelt
476db6ef39
Move to a newer Scala version
...
Chisel3 needs a newer version of Scala to run correctly.
2016-03-24 12:00:13 -07:00
Howard Mao
be8a411f9c
get rid of axe submodule and move toaxe.py script to scripts
2016-02-29 10:59:19 -08:00
Howard Mao
8a877fa620
Add Matthew Naylor's trace generator and AXE scripts
2016-02-24 14:39:11 -08:00
Palmer Dabbelt
c9a2b7d109
Add torture as part of the regression
...
Since the latest Spike fix my torture runs are succeeding, so I can now run it
as part of the regression flow.
2016-01-31 23:06:59 -08:00
Howard Mao
55581195eb
add groundtest submodule for simple memory testing
2015-11-11 14:33:02 -08:00
Henry Cook
47bc193c16
added CDE library as submodule
2015-10-21 18:24:16 -07:00
Henry Cook
51c42083d0
Add new junctions repo as submodule (contains externally facing buses and peripherals).
...
Bump all submodules.
2015-07-29 18:15:45 -07:00
Yunsup Lee
09e29e8fe0
add zscale
...
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
2015-07-07 20:38:47 -07:00
Yunsup Lee
5ca7f08226
change rocket submodule
2014-10-07 03:19:48 -07:00
Yunsup Lee
e1b8f69cb5
change submodule pointers to https
2014-10-07 03:16:20 -07:00
Scott Beamer
06bc6a45db
move fpga repo to git@ from https
2014-10-06 13:45:09 -07:00
Yunsup Lee
6c18cd9559
add new fpga-zynq as submodule
2014-09-30 09:32:02 -07:00
Yunsup Lee
3175a40509
add berkeley-hardfloat as submodule
2014-09-08 00:18:49 -07:00
Yunsup Lee
1e5b2f658f
remove existing hardfloat repository
2014-09-07 23:45:47 -07:00
Henry Cook
9b36162b67
Point rocket/ to rocket-staging repo
2014-08-19 14:20:15 -07:00
Henry Cook
fc9c676fc1
add chisel and hardfloat back as sub-projects, bump other sub-projects
2013-09-26 12:01:46 -07:00
Henry Cook
b06d33da2f
Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
2013-08-19 19:54:41 -07:00
Yunsup Lee
5b55cc93af
add submodule riscv-tools
2013-05-10 11:53:55 -07:00
Miquel Moreto
5d75ddc553
Added dramsim2 memory model to the emulator backend
2012-10-14 14:06:28 -07:00
Huy Vo
084a0d31c3
initial commit, all the relevant submodules
2012-09-26 17:46:17 -07:00
