add zscale

only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
2015-07-07 20:38:47 -07:00
parent e6a13cdeba
commit 09e29e8fe0
5 changed files with 79 additions and 5 deletions
--- a/.gitmodules
+++ b/.gitmodules
@ -19,3 +19,6 @@
 [submodule "fpga-zynq"]
 	path = fpga-zynq
 	url = https://github.com/ucb-bar/fpga-zynq.git
+[submodule "zscale"]
+	path = zscale
+	url = https://github.com/ucb-bar/zscale