riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,250 Commits 1 Branch 0 Tags 13 MiB
1d8e539362
Commit Graph

5250 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andrew Waterman
938b089543 Remove legacy devices that use AMOALU 
I'm going to change the AMOALU API, and so I'm removing dependent dead code.
 2017-05-02 03:05:41 -07:00
Andrew Waterman
f8151ce786 Remove subword load muxing in ScratchpadSlavePort 2017-05-02 00:14:46 -07:00
Andrew Waterman
044b6ed3f9 Improve logical ops in AMOALU 
As with integer ALU, shave off some muxing.
 2017-05-02 00:14:46 -07:00
Andrew Waterman
f49172b5bc ScratchpadSlavePort doesn't support byte/halfword atomics 2017-05-02 00:14:46 -07:00
Wesley W. Terpstra
fe280187a1 axi4: Fragmenter cuts all input channel readys 
AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
3d06f01a2c rocket: turn on early ack for ITIM 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
58a4529cc5 axi4: the last missing piece for safe FIFO ordering 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
b0b5601e8d axi4: ToTL correct error handling 
If there is an illegal AWADDR = 0x2 on a 32-bit bus, remapping it
to an aligned address on the error device may make the mask
inconsistent with the address + size.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
661015a78d axi4: switch arbiter to round robin 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
976af7a8c7 tilelink2: better width inference for {left,right}OR 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
40f18e6e43 diplomacy: optimize IdRange overlap detection 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
30f1f1e7c7 rocket: turn on early ack for DTIM 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
6ee69454c3 tilelink2: Fragmenter now supports early Ack 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
e09fa866b7 tilelink2: FIFOFixer should NOT change client request status 
Just because some clients are not FIFO does not matter. Downstream
FIFOFixers will still present a legitimate single domain to those
client who care.
 2017-05-01 22:53:41 -07:00
Scott Johnson
b040a462c9 Wes's change to remove user bits from external AXI interface, and add 1 cycle latency to make sure external AXI is compliant 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
a71f708dc7 rocketchip: move the Error device to 0x3000 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
d27e1928dd axi4: make maxFlight a per-master parameter 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e1a072a644 axi4: massage test cases into shape again 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
9f08c484bd tilelink2: ToAXI4 provide FIFO order semantics 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
61a6f94196 axi4: get unit tests legal again 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
bf5cb396b9 rocketchip: relax mmio no-interleaving requirement 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
24f577c156 axi4: Deinterleaver ensures R channel ID does not change till last 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
b4188ee625 axi4: ToTL supporting pipelined MMIO 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
ca2cb033cd rocketchip: fix uses of AXI4 Fragmenter 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e100a943ea axi4: simplify Fragmenter by using user bits 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
7a1d107c9e rocketchip: include an ErrorSlave by default 2017-05-01 22:53:37 -07:00
Wesley W. Terpstra
641a4d577a tilelink2: Error device for returning errors on demand 2017-05-01 22:53:02 -07:00
Wesley W. Terpstra
a580b17ece axi4: IdIndexer => reduce number of needed ids 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
06efc01d96 axi4: an adapter to remove user bits 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
f1217519f1 axi4: RegisterRouter; concurrent response illegal in AXI 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
5163ccd11f axi4: RegisterRouter supports user bits 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
de6ea9b442 axi4: support user bits in SRAM 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
396ecacda4 AXI4: add an optional user bundle field 2017-05-01 22:53:01 -07:00
Andrew Waterman
d6e69066a5 Fix ITIM loads (#716) 
An incorrectly-set ready signal caused bad data to be read from the RAM.
 2017-05-01 17:41:25 -07:00
Andrew Waterman
dd85d7e0a0 I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle 
@solomatnikov found the bug.  It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
 2017-04-28 16:44:58 -07:00
Megan Wachs
d67738204f Interrupts: Less Pessimistic Synchronization (#714) 
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
 2017-04-28 14:49:24 -07:00
Andrew Waterman
9b688ce7e2 Merge pull request #707 from ucb-bar/itim 
ITIM
 2017-04-28 02:55:01 -07:00
Andrew Waterman
7416f2a17e Unbreak groundtest 2017-04-28 02:10:33 -07:00
Andrew Waterman
8fd5ecdff8 Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR 2017-04-27 19:50:38 -07:00
Andrew Waterman
7c70aa593e Minor stylistic and QoR improvements to PLIC 2017-04-27 19:35:20 -07:00
Henry Cook
3d0ed80ef6 new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels 2017-04-27 18:17:31 -07:00
Henry Cook
bdb526a9f0 coreplex: DefaultCoreplex => RocketPlex 2017-04-27 18:17:09 -07:00
Andrew Waterman
99de42d34c Swap order of ITIM WidthWidget and Fragmenter 
e99fa057ac accidentally reversed them
 2017-04-27 15:30:02 -07:00
Andrew Waterman
8c10caeef9 Express PMP mask generation with incrementer, not adder 
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
 2017-04-27 15:16:29 -07:00
Henry Cook
e99fa057ac cleanup scratchpad nodes 2017-04-27 14:02:05 -07:00
Andrew Waterman
b2b4725522 Fix zero-width wire issues when ITIM is disabled 2017-04-26 22:43:00 -07:00
Andrew Waterman
e23ee274f6 Size hartid field with NTiles, not XLen 2017-04-26 20:11:43 -07:00
Andrew Waterman
dc753bfa95 Fix I$ elaboration when ITIM is disabled 2017-04-26 19:35:35 -07:00
Andrew Waterman
80d826b94a Make DTIM deduplicatable 2017-04-26 19:35:35 -07:00
Andrew Waterman
418879a47f Add Instruction Tightly Integrated Memory 2017-04-26 19:35:35 -07:00