riscv/rocket-chip
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176110b6d3
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1800 Commits

Author SHA1 Message Date
Andrew Waterman
176110b6d3 Don't trigger ECC writebacks when a release is in flight 2017-08-12 15:23:57 -07:00
Wesley W. Terpstra
f191bb994c PatternPusher: can now expect a certain output (#952) 2017-08-11 18:10:27 -07:00
Wesley W. Terpstra
baf769f924 tilelink: add PatternPusher, a device to inject a fixed traffic pattern (#950) 2017-08-11 15:07:10 -07:00
Andrew Waterman
a3358f34a0 Fix priority inversion for two back-to-back divides (#948) 
If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit.  While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
 2017-08-10 17:12:09 -07:00
Andrew Waterman
0a591c5b5b Roll back use of UIntToOH1 (#946) 
These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass.  This is not yet conclusive.
 2017-08-09 18:39:47 -07:00
Andrew Waterman
721770244e Fix IBuf bug 
Don't examine a packet's xcpt signal if it might be invalid.  In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
 2017-08-09 09:47:51 -07:00
Wesley W. Terpstra
a9b1410f01 BusBlocker: parameterize page granularity 2017-08-08 17:10:01 -07:00
Wesley W. Terpstra
010ba94474 BusBlocker: rename a variable 2017-08-08 17:00:22 -07:00
Wesley W. Terpstra
6d6fc38787 BusBlocker: lock bit should affect the prior PMP address, not next 2017-08-08 17:00:12 -07:00
Andrew Waterman
809c7e8551 Don't merge stores that manifest WAW hazards 
The following sequence would drop the first store when eccBytes=4:

    sb x0, 0(t0)
    nop
    sb x0, 4(t0)
    nop
    sb x0, 1(t0)

Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
 2017-08-08 15:19:05 -07:00
Wesley W. Terpstra
3ef6e4c9f2 Merge pull request #939 from freechipsproject/bus-blocker 
tilelink: PMP controlled BusBlocker prevents bus accesses
 2017-08-08 15:06:55 -07:00
Andrew Waterman
82e13443b2 Merge pull request #937 from freechipsproject/critical-paths 
Perform tag error detectoin/correction in same cycle as RAM
 2017-08-08 15:03:28 -07:00
Wesley W. Terpstra
8f261adc6b BusBlocker: change default policy to deny 2017-08-08 14:19:59 -07:00
Wesley W. Terpstra
0d76e96b88 tilelink: PMP controlled BusBlocker prevents bus accesses 2017-08-08 13:28:01 -07:00
Andrew Waterman
7935c61c19 Don't report to the DTIM that data is cacheable 
Otherwise, it will attempt to perform AMOs where they're unsupported!
 2017-08-08 11:55:04 -07:00
Andrew Waterman
74d309c18e Make I vs. D a static property of TLB, not an input pin 
The microarchitecture doesn't really support unified TLBs, so don't fake it.
 2017-08-08 11:54:47 -07:00
Andrew Waterman
e92981b0bd DRY 2017-08-08 11:46:38 -07:00
Andrew Waterman
62ccba304c Perform tag error detectoin/correction in same cycle as RAM 
The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
 2017-08-08 10:21:30 -07:00
Palmer Dabbelt
6d1d285464 Merge pull request #933 from freechipsproject/cinst 
Print out the compressed instruction when executing one
 2017-08-07 21:40:10 -07:00
Palmer Dabbelt
cc1e2af336 Merge pull request #934 from freechipsproject/critical-paths 
Revert "Remove one gate from D$ ECC check"
 2017-08-07 19:41:08 -07:00
Henry Cook
c8f8806df0 Merge pull request #932 from freechipsproject/tl-bus-delayer 
tilelink: allow insertion of TLDelayer on TLBus outward node
 2017-08-07 19:01:39 -07:00
Henry Cook
c4092dd0cc tilelink: improve entropy of bus delayer 2017-08-07 17:36:07 -07:00
Andrew Waterman
402907990c Revert "Remove one gate from D$ ECC check" 
This reverts commit 7d94074b05, which
works fine with optimistic behavioral RAMs but not real ones.
 2017-08-07 17:33:20 -07:00
Henry Cook
2910d6fa2a tilelink: make bus xbar protected so it can be suggestNamed 2017-08-07 17:30:24 -07:00
Palmer Dabbelt
fc0d5fcf98 Print out the compressed instruction when executing one 2017-08-07 17:21:53 -07:00
Wesley W. Terpstra
e27072e063 Merge pull request #931 from freechipsproject/fix-ram-model-source-reuse 
Fix ram model source reuse
 2017-08-07 16:56:13 -07:00
Henry Cook
c457c9cb9f tilelink: allow insertion of TLDelayer on TLBus outward node 2017-08-07 16:43:06 -07:00
Wesley W. Terpstra
f8b45564d1 tilelink: RAMModel must support source reuse 
If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
 2017-08-07 16:01:15 -07:00
Yunsup Lee
558fc7f293 maskrom: retain data for d channel is not ready 2017-08-07 12:17:10 -07:00
Andrew Waterman
7fd8bb1159 Merge pull request #928 from freechipsproject/critical-paths 
Critical paths
 2017-08-06 18:50:59 -07:00
Andrew Waterman
658e36f98b Reduce fanout on frontend io.cpu.req.valid signal 2017-08-06 17:38:51 -07:00
Andrew Waterman
7d94074b05 Remove one gate from D$ ECC check 
The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
 2017-08-06 17:36:53 -07:00
Wesley W. Terpstra
d03fdc4f30 diplomacy: seal the LazyModuleImpLike trait (#927) 
This makes sure that all the base classes call instantiate()
 2017-08-06 17:32:23 -07:00
Yunsup Lee
aa60c6944b diplomacy: provide default clock/reset for LazyRawModuleImp 2017-08-06 13:40:07 -07:00
Andrew Waterman
83875e3a0c Only flush D$ on FENCE.I if it won't always be probed on I$ miss 2017-08-05 14:22:40 -07:00
Andrew Waterman
991e16de92 Remove probe address mux from TLB response path 2017-08-05 12:57:38 -07:00
Andrew Waterman
b9b4142bb4 Get s2_nack off the critical path 
We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively).  This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
 2017-08-05 00:30:36 -07:00
Andrew Waterman
bc298bf146 Optimize ShiftQueue for late-arriving deq.ready 2017-08-04 22:06:37 -07:00
Andrew Waterman
6112adfbb0 Get L2 TLB tag/parity check off the D$ arbitration path 2017-08-04 17:01:51 -07:00
Andrew Waterman
8d97684555 Fix L2 TLB perfctr 
It was counting conflict misses but not cold misses.
 2017-08-04 17:01:31 -07:00
Andrew Waterman
df7f09b9ce Get I$ ECC check further off critical path 2017-08-04 16:59:21 -07:00
Andrew Waterman
4bfbe75d74 Avoid pipeline replays when fetch queue is full 2017-08-04 16:59:21 -07:00
Andrew Waterman
a45997d03f Separate I$ parity error from miss signal 
Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
 2017-08-04 16:59:21 -07:00
Andrew Waterman
06a831310b Shave a gate delay off I$ backpressure path 
The deleted code was a holdover from Hwacha's vector fences.
 2017-08-04 13:12:43 -07:00
Andrew Waterman
ecc2ee366c Shave a few gate delays off IBuf control logic 
It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.
 2017-08-04 13:12:43 -07:00
Andrew Waterman
7937db0c84 Merge pull request #919 from freechipsproject/imiss-perf-counter 
Fix I$ miss perfctr
 2017-08-04 01:04:23 -07:00
Megan Wachs
017ac130c1 Merge pull request #922 from freechipsproject/bigger_tl_xbar 
TLXbar: Allow more masters and slaves and issue a warning.
 2017-08-03 16:52:56 -07:00
Megan Wachs
50c85f1b62 TLXbar: Allow more masters and slaves and issue a warning. 2017-08-03 15:46:06 -07:00
Andrew Waterman
ba4eecc0f0 Use UIntToOH1 (#921) 
Closes #920
 2017-08-03 14:55:39 -07:00
Andrew Waterman
f483bab4aa Fix I$ miss perfctr 
The old version was counting prefetches, too.
 2017-08-03 00:52:12 -07:00