Andrew Waterman
25e1412a33
Merge pull request #11 from ucb-bar/regression-fixes
...
Regression script fixes
2015-07-20 12:58:54 -07:00
Palmer Dabbelt
d6b29ca9cc
Run regression with bash's "-ex" mode
...
This causes every command to be echo'd to stderr, and any failing
command will fail the whole script. Without this the regression
script will always pass.
2015-07-20 12:21:19 -07:00
Palmer Dabbelt
9bbecffbb8
Have regression run "make" before "make run-asm-tests"
...
I'm seeing some odd behavior where "make run-asm-tests" actually does
nothing. This works around the issue.
2015-07-20 12:20:32 -07:00
Yunsup Lee
a99b1e3a01
append config name to generated Makefrag filename
2015-07-17 12:34:49 -07:00
Yunsup Lee
777facf91e
update tools
2015-07-17 12:33:19 -07:00
Yunsup Lee
e7802825c3
add Zscale testing
2015-07-17 12:02:02 -07:00
Henry Cook
1e977d12f2
Update README.md
2015-07-15 16:25:04 -07:00
Yunsup Lee
4c7c3f5bb2
add test generate for ZscaleTop
2015-07-14 16:26:28 -07:00
Yunsup Lee
d6df479870
move 'include /Makefrag' out of top-level Makefrag
2015-07-14 16:13:32 -07:00
Henry Cook
76046c52fe
Cleanup testing rv64uf
2015-07-13 18:58:58 -07:00
Henry Cook
186e32a546
Merge pull request #9 from ucb-bar/param-based-makefrags
...
Param-based makefrag generation
2015-07-13 15:51:28 -07:00
Henry Cook
302cd3e638
Added BuildZscale param for use in Top and makefrag generation
2015-07-13 15:46:42 -07:00
Henry Cook
407d8e473e
first cut at parameter-based testing
2015-07-13 14:54:26 -07:00
Henry Cook
4e4015089d
rename Configs source
2015-07-09 15:04:11 -07:00
Henry Cook
3573fcdf2d
bump uncore
2015-07-09 14:42:38 -07:00
Yunsup Lee
09e29e8fe0
add zscale
...
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
2015-07-07 20:38:47 -07:00
Yunsup Lee
e6a13cdeba
New machine-mode timer facility
...
Mirroring Andrew's commit to reference-chip
2015-07-07 17:26:07 -07:00
Henry Cook
4fbb0f80ff
Added some multicore/multibanks named ChiselConfigs
2015-07-06 18:21:06 -07:00
Henry Cook
854fd64fba
Added optional Makefile includes for private chip repos
2015-07-06 17:15:27 -07:00
Henry Cook
d3ccec1044
Massive update containing several months of changes from the now-defunct private chip repo.
...
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
Scott Beamer
12d8d8c5e3
Merge pull request #8 from seldridge/master
...
Fix FPGA/VLSI Mem Gen for Python 2 and 3 Environments
2015-06-28 08:54:24 -05:00
Schuyler Eldridge
b4cd8c5981
Fix vlsi_mem_gen for Python 2 or 3
2015-06-25 12:48:31 -07:00
Schuyler Eldridge
a42832fc70
Fix fpga_mem_gen for Python 2 and 3 Environments
...
Two quick fixes that enable fpga_mem_gen to work with either Python 2 or
Python 3:
* Change an `xrange` instance to `range`
* Wrap the arguments of a bare `print` in parentheses
2015-06-25 11:03:33 -07:00
Scott Beamer
a59ba39310
bump submodule for fpga-zynq
2015-05-21 11:26:57 -07:00
Scott Beamer
38edbc78e5
Merge pull request #5 from amsharifian/master
...
Update Makefile
2015-05-21 11:24:25 -07:00
Amirali Sharifian
879a4a0bcd
Update Makefile
...
Change default shell to bash shell.
2015-04-06 15:05:43 -07:00
Yunsup Lee
4f57985198
change organization to riscv
2015-02-17 14:43:11 -08:00
Albert Magyar
09cd555f29
Update riscv-tools pointer to prepare for HPCA workshop.
2015-02-04 13:29:04 -08:00
Scott Beamer
2a5dd907f5
bump chisel version
2015-01-06 16:59:10 -08:00
Yunsup Lee
170f1fecbc
push chisel,rocket,riscv-tools
2014-10-21 12:32:58 -07:00
Yunsup Lee
1b31931981
Merge pull request #2 from wasserfuhr/patch-1
...
Update README.md
2014-10-07 17:02:55 -07:00
RainerWasserfuhr
9b41ad92ba
Update README.md
...
typo?
2014-10-08 01:46:48 +02:00
Yunsup Lee
f15baeea49
fix markdown for webpage
2014-10-07 03:55:00 -07:00
Yunsup Lee
5ca7f08226
change rocket submodule
2014-10-07 03:19:48 -07:00
Yunsup Lee
e1b8f69cb5
change submodule pointers to https
2014-10-07 03:16:20 -07:00
Yunsup Lee
447761b06c
fix typo in README
2014-10-07 02:09:34 -07:00
Yunsup Lee
91f211f766
updates to README
2014-10-07 02:08:03 -07:00
Yunsup Lee
702ddabe26
add ExampleSmallConfig for README
2014-10-07 02:07:59 -07:00
Yunsup Lee
ae9b78d9ef
add what/how explanation to README
2014-10-07 02:07:39 -07:00
Scott Beamer
5f55ded723
bump fpga submodule
2014-10-06 13:45:12 -07:00
Scott Beamer
06bc6a45db
move fpga repo to git@ from https
2014-10-06 13:45:09 -07:00
Henry Cook
23ae6893ad
bump chisel
2014-10-06 13:45:03 -07:00
Yunsup Lee
e25d420155
Improve ChiselConfig composability; bump chisel
2014-10-06 13:43:40 -07:00
Yunsup Lee
73eac94a65
Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
2014-10-06 13:40:35 -07:00
Henry Cook
f97a801d60
Parameter API update
2014-10-06 13:37:42 -07:00
Henry Cook
122733b3a9
file name consistency
2014-10-06 13:37:38 -07:00
Henry Cook
a9d72aac2a
bump rocket
2014-10-06 13:37:27 -07:00
Henry Cook
0b5f23a209
Streamlined uncore for release
2014-10-06 13:37:15 -07:00
Yunsup Lee
6c18cd9559
add new fpga-zynq as submodule
2014-09-30 09:32:02 -07:00
Yunsup Lee
7a28d2b47c
forgot to move more hwacha stuff out in rocket-chip
2014-09-25 15:34:18 -07:00
