Henry Cook
fe287864ef
bump firrtl
2017-03-13 13:14:16 -07:00
Henry Cook
1a3fec61c0
Merge branch 'master' into priv-1.10
2017-03-13 11:59:18 -07:00
Wesley W. Terpstra
d2da33e4b1
Fuzzer: use different LFSR seeds based on simulator seed
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
bb6108abd5
Tests: include more random delays
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
0c7fb87390
TLDelayer: insert noise on invalid cycles
2017-03-11 02:53:43 -08:00
Jacob Chang
1c6dde8c15
Make parameters for TLToAHB and TLToAXI4 accessable ( #581 )
2017-03-10 22:26:38 -08:00
Henry Cook
dbc8f4b30b
last => done
2017-03-10 15:58:38 -08:00
Andrew Waterman
380c10f7bd
Zap conflicting TLB entries, preparing for superpage support
...
Superpages create the possibility that two entries in the TLB may match.
This corresponds to a software bug, but we can't return complete garbage;
we must return either the old translation or the new translation. This
isn't compatible with the Mux1H approach. So, flush the TLB and report
a miss on duplicate entries.
2017-03-10 15:58:23 -08:00
Andrew Waterman
b24c43badb
Don't double-count release traffic in perfctrs
2017-03-09 16:49:02 -08:00
Andrew Waterman
63f8ce36f6
Avoid VM exceptions in groundtest by setting Accessed bit
2017-03-09 16:48:28 -08:00
Andrew Waterman
4f8f05d635
Add performance counter facility
2017-03-09 13:58:50 -08:00
Andrew Waterman
e57ee2692d
bump tools
2017-03-09 13:58:40 -08:00
Andrew Waterman
33b6d48376
Fix haltnot reporting (previously always returned 0)
2017-03-09 13:58:40 -08:00
Andrew Waterman
24a2278fc4
Perform all illegal-instruction detection in ID stage
...
This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
2017-03-09 11:29:51 -08:00
Andrew Waterman
7668827741
Support unrolling the integer divider
2017-03-09 11:29:51 -08:00
Andrew Waterman
74d8d672bf
Improve BTB critical path at slight accuracy cost
...
Make entries fully associative on lower 14 bits only, not full address.
2017-03-09 11:29:51 -08:00
Andrew Waterman
11c8857b5d
Don't re-read I$ RAMs on stall
2017-03-09 11:29:51 -08:00
Andrew Waterman
db0a02b78e
WIP on priv-1.10
2017-03-09 11:29:51 -08:00
Wesley W. Terpstra
43dea38ee9
dcache: we need the bits within the beat so select the right word ( #575 )
...
We now have confirmation that it fixed the problem.
2017-03-08 00:19:09 -08:00
Andrew Waterman
603b8af2eb
Don't canonicalize 32-bit FP results in the various pipelines
...
It's redundant with the new scheme, so just adds HW for no reason.
2017-03-07 20:51:32 -08:00
Andrew Waterman
f505aba1ac
Use sNaN value for flw, like other single-precision ops
2017-03-07 20:51:32 -08:00
Andrew Waterman
cc389bea90
Fix in-register representation of fdiv.s/fsqrt.s result
...
We were zero-extending it, which is a double-precision zero in the recoded
format. So, when spilled and reloaded with fsd/fld, the original value
was destroyed. Instead, set the MSBs so that it represents sNaN. When
spilled, the single-precision number will be preserved as the NaN payload.
2017-03-07 20:51:32 -08:00
Henry Cook
4af437fdab
RANDOMIZE_MEM_INIT vlsi_mem_gen ( #572 )
2017-03-07 01:56:15 -08:00
Henry Cook
d0ae087587
rocket: allow scratchpad address to be configurable ( #570 )
2017-03-06 21:35:45 -08:00
Henry Cook
229fb2251d
coreplex: hack to fix tile dedup ( #569 )
2017-03-06 16:36:03 -08:00
Henry Cook
33ffb62326
Merge pull request #568 from ucb-bar/elide-empty-int-ext
...
PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0
2017-03-03 12:46:11 -08:00
Wesley W. Terpstra
676974281a
rocket: describe dcache scratchpad as memory
2017-03-03 02:54:48 -08:00
Wesley W. Terpstra
1eeaa390c6
diplomacy: output JSON formatted version of DTS
2017-03-03 02:45:11 -08:00
Wesley W. Terpstra
0178248551
diplomacy: evaluate ResourceBindings only once
2017-03-03 02:04:17 -08:00
Wesley W. Terpstra
8e4f348dda
rocket: if no MMU, don't print it in DTS
2017-03-03 00:48:26 -08:00
Wesley W. Terpstra
7660be039c
rocketchip: add WithTimebase to set RTC frequency
2017-03-03 00:47:50 -08:00
Wesley W. Terpstra
57a329408c
PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0
2017-03-03 00:28:55 -08:00
Wesley W. Terpstra
46369850cf
Merge pull request #567 from ucb-bar/dts
...
Dts - Device Tree Output
2017-03-02 21:51:51 -08:00
Wesley W. Terpstra
4535de2669
rocket: use diplomatic interrupts
...
This makes it possible for the PLIC to work with heterogenous cores.
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
d3c5318714
build: remove the now obsolete config string
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
93ca555c20
IntXing: support configurable sync depth
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
637bc6c3a7
coreplex: pretty print discontiguous ranges properly
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
7ff9f88ad7
rocket: connect interrupt map for Plic+Clint
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
38489ad9b0
tilelink2: bring IntNode parameters up to the current standard
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
5bd9f18e5b
rocket: add dts cpu description
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
cfd367248f
rocketchip: add blind ports to DTS
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
9a5e2e038b
uncore: add DTS meta-data for devices
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
0b950b5938
coreplex: bind assigned resources
2017-03-02 21:19:19 -08:00
Wesley W. Terpstra
7f6a250dbf
tilelink2: add hooks for Resources
2017-03-02 21:19:19 -08:00
Wesley W. Terpstra
e322692d16
diplomacy: add DeviceTree renderer
2017-03-02 21:19:14 -08:00
Wesley W. Terpstra
c01a74f4a0
diplomacy: add AddressRange conversion to/from AddressSet
2017-03-02 11:14:28 -08:00
Wesley W. Terpstra
bb70b1a3c3
diplomacy: add resource tracking
2017-03-02 11:14:28 -08:00
Henry Cook
3a55a1afae
Merge pull request #562 from ucb-bar/periphery-adjustments
...
Periphery adjustments
2017-03-02 11:14:07 -08:00
Henry Cook
9544b8007e
bump chisel3
2017-03-02 10:41:26 -08:00
Henry Cook
9ce6898d46
firrtl: bump firrtl
2017-03-01 16:58:29 -08:00
