3780 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
Henry Cook	0e30364f56	WIP	2016-11-14 13:39:01 -08:00
Henry Cook	c0efd247b0	[tl2] expand firstlast api and L1WB bugfix	2016-11-14 12:12:31 -08:00
Henry Cook	b7730d66f2	WIP bugfixes: run until corrupted WB data (beats repeated)	2016-11-11 18:34:48 -08:00
Henry Cook	71315d5cf5	WIP scala compile and firrtl elaborate; monitor error	2016-11-11 13:07:45 -08:00
Henry Cook	afa1a6d549	WIP uncore and rocket changes compile	2016-11-10 15:57:29 -08:00
Wesley W. Terpstra	32fd11935c	rocketchip: use TL2 and AXI4 for memory subsytem	2016-11-04 13:36:47 -07:00
Wesley W. Terpstra	9d77e34bee	tilelink2 Filter: make transfer cap robust against large filters	2016-11-04 13:35:36 -07:00
Wesley W. Terpstra	4a2cf6431b	coreplex: make 'mem' port an Option until we can use a Seq	2016-11-04 13:35:36 -07:00
Wesley W. Terpstra	8f757a9135	coreplex: rename BankedL2 trait to BankedL2CoherenceManagers	2016-11-04 13:35:36 -07:00
Wesley W. Terpstra	b8df59f43b	tilelink2 Broadcast: support "bufferless" implementation	2016-11-04 13:35:36 -07:00
Wesley W. Terpstra	14800f8fb4	tilelink2 Broadcast: only support caching readable devices	2016-11-04 13:35:36 -07:00
Wesley W. Terpstra	d03046d11c	coreplex: fix BankedL2 line width	2016-11-04 13:35:36 -07:00
Wesley W. Terpstra	ea602790a8	Merge pull request #432 from ucb-bar/tl2-address-filtering ... Tl2 address filtering	2016-11-04 00:12:43 -07:00
Wesley W. Terpstra	da3cc3b299	coreplex: TileLink2 l1tol2 memory channels	2016-11-03 22:18:28 -07:00
Wesley W. Terpstra	0f3947bb86	tilelink2 Broadcast: add special case handling for 0 cached clients	2016-11-03 22:18:28 -07:00
Wesley W. Terpstra	ba3c83287f	tilelink2 Xbar: merge the AddressSets of fractured managers	2016-11-03 22:18:28 -07:00
Wesley W. Terpstra	55326c29bb	tilelink2: Filter adapter removes some of the address space	2016-11-03 22:18:23 -07:00
Wesley W. Terpstra	163b7577bd	Merge pull request #431 from ucb-bar/tl2-broadcast ... Tl2 broadcast	2016-11-03 15:39:43 -07:00
Wesley W. Terpstra	86ba94781b	tilelink2: broadcast coherence manager	2016-11-03 14:37:19 -07:00
Wesley W. Terpstra	d067e87a7d	tilelink2 Parameters: sinkId is per port, not per manager	2016-11-03 14:37:17 -07:00
Wesley W. Terpstra	1b016051e8	Merge pull request #424 from ucb-bar/coreplex-cake ... Coreplex cake	2016-10-31 16:49:27 -07:00
Wesley W. Terpstra	ed4224dde4	tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull ... If we send out the PutFull portion of an AMO, the slave is allowed to respond with AccessAck on the same cycle. In this case, we are still in the AMO state, but must still match the D response.	2016-10-31 15:17:10 -07:00
Wesley W. Terpstra	f83d1d0aaf	coreplex: rename trait CoreplexRISCVPlatform ... This makes it clear we are talking about the devices one expects in the platform, not the ISA.	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	f943c5d6ef	rocketchip: connect rtcTick to coreplex	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	4a0b29850c	coreplex: reattach clint interrupt	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	a12fea51e8	Plic: skip reserved interrupt in interrupt map printout	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	aabd17d935	rocketchip: must create bundles within Module scope ... 1. Bundles be created after base class Module constructor runs 2. Bundles must be created before Module(...) runs Solution: pass a bundle constructor to the cake base class Require the constructor to take a parameter so people don't use it by accident; they should get a type error. Consistently name all the cake arguments with an _io, _coreplex, _outer, so that they don't shadow the base class variables you should be using.	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	d52615c39e	coreplex: one IntNode per tile	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	e97844f71e	coreplex: make it possible to override the ConfigString	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	4de1822470	rocketchip: avoid using the nearly defunct GlobalAddrMap	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	688e1bffdf	rocketchip: pull rtcTick out of the coreplex	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	5bca13ebdb	rocketchip: use self-type constraints	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	d51b0b5c02	rocketchip: use self-type	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	841a31479a	coreplex: fix TinyConfig	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	ba529c3716	rocketchip: use TileLink2 interrupts	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	6505431eac	coreplex: use self-type constraints	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	ac886026e6	rocketchip: reduce number of type parameters	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	043ed48c8c	tilelink2 HintHandler: delay answers to help TL1 legacy clients	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	72a7948ad2	rocketchip Periphery: move atomics before WidthWidget => 64-bit AMOs	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	015c3b862a	diplomacy: print out bus widths on edges in agent graph	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	92ee498521	rocket scratchpad: support atomics	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	0cc00e7616	regressions: test scratchpad	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	d2e9fa8ec6	Plic: remove path from ready to bits	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	545154c1c3	groundtest: make it happy with TL2 addressing	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	9a26cb7ec7	Debug: mark the debug device executable	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	e9725aea2f	rocketchip: all of the address map now comes from TL2	2016-10-31 11:42:44 -07:00
Wesley W. Terpstra	401fd378b4	rocketchip: include devices from cbus in ConfigString	2016-10-31 11:42:13 -07:00
Wesley W. Terpstra	b68bc449e7	rocket: put a Fragmenter infront of the scratchpad	2016-10-31 11:42:13 -07:00
Wesley W. Terpstra	a73aa351ca	rocketchip: fix all clock crossings	2016-10-31 11:42:13 -07:00
Wesley W. Terpstra	825c253a72	rocketchip: move TL2 and cake pattern into Coreplex	2016-10-31 11:42:13 -07:00