Colin Schmidt
ad81d95751
add run-asm-{p,pt,v}-tests targets for convenience
2016-02-24 19:49:35 -08:00
John Wright
b04cd545b6
pass base SCR address to SCRFile for address calculation
2016-02-24 15:32:46 -08:00
Howard Mao
8a877fa620
Add Matthew Naylor's trace generator and AXE scripts
2016-02-24 14:39:11 -08:00
Howard Mao
8c02cb09ca
some additions to Travis and fixes for Testing
2016-02-23 23:37:29 -08:00
Palmer Dabbelt
c263c636b3
Actually reference all the tests from RISCV
2016-02-23 16:05:27 -08:00
Palmer Dabbelt
bae4c0c0c9
Point Testing to $RISCV/... not $base_dir/...
...
This uses the compiled tests in RISCV, which match the rest of the toolchain.
2016-02-23 10:58:51 -08:00
Colin Schmidt
4ce603e548
Memtest configs should not have a hex file loaded
2016-02-22 12:49:26 -08:00
Colin Schmidt
0c575403af
only use a single asm test and 1 bmark for memtest
2016-02-22 09:36:53 -08:00
Howard Mao
5e4a02038c
move FPGA AXI to HTIF converter into Chisel module
2016-02-19 13:53:31 -08:00
Palmer Dabbelt
926efd0cab
Allow the number of memory channels to be picked at runtime
...
We're building a chip with 8 memory channels. Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels. This commit adds a SCR that controls the number of active
memory channels on a chip. Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.
By default this just adds a 1-bit SCR, which essentially no extra logic.
When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration. The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.
A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
2016-02-17 15:23:30 -08:00
Palmer Dabbelt
db9de94588
Generate and use SCR address header files
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This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
Christopher Celio
c1b4d9372f
Revert "add new parameters for new SCR file"
...
This reverts commit 4dad5b8b32
2016-02-13 04:02:20 -08:00
Christopher Celio
6c6bbca92a
Revert "use singleton for global"
...
This reverts commit 4d0f941de3
2016-02-13 03:56:47 -08:00
John Wright
4d0f941de3
use singleton for global
2016-02-13 00:56:11 -08:00
John Wright
4dad5b8b32
add new parameters for new SCR file
2016-02-12 18:24:12 -08:00
Howard Mao
9fb2216548
get rid of unused external mmio port
2016-02-10 21:49:02 -08:00
Howard Mao
72a876bfba
add NASTI to TL converter
2016-02-10 11:12:39 -08:00
Palmer Dabbelt
b2ed35e8aa
Print a better error on missing config classes
...
Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.
2016-02-05 09:59:02 -08:00
Palmer Dabbelt
8422aaf6fc
Add a "/" when targetDir doesn't have one
...
This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.
2016-02-05 09:57:47 -08:00
Palmer Dabbelt
3bb0f11e6c
Chisel3 <> reverse fix
2016-02-05 09:56:42 -08:00
Howard Mao
06c3f9b655
Rocket Chip fixes in response to lowRISC team's comments
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* DMA frontend-backend communication tunneled over TileLink/AXI
* Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
* Don't make NIOMSHRs configurable. Fixed at 1.
* Connect accelerator-internal CSRs into the CSR file
* Make mtvec register configurable and writeable
2016-02-02 13:14:52 -08:00
Howard Mao
33aa64212d
fix more Chisel3 deprecations
2016-01-14 15:06:30 -08:00
Howard Mao
c06884b78c
lowercase SMI to Smi
2016-01-11 17:44:10 -08:00
Howard Mao
806e40d19b
implement DMA streaming functionality
2016-01-07 19:26:15 -08:00
Howard Mao
8190bf6e18
implement DMA unit
2015-12-16 21:27:48 -08:00
Howard Mao
1a272677ca
more fixes to L2 cache
2015-12-16 21:06:39 -08:00
Howard Mao
560fdc19a8
add PLRU replacement option to L2 cache
2015-12-16 10:24:57 -08:00
Howard Mao
7ad9deeaee
Fix issues with request merging in L2 cache and add regression tests
...
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
2015-12-15 23:02:15 -08:00
Howard Mao
0c91e00676
move GroundTest configs to a separate file
2015-12-06 03:01:05 -08:00
Howard Mao
4f5dabcda2
add SCR file to device tree
2015-12-05 00:28:58 -08:00
Howard Mao
f35b83d3ca
allow configuration of rocket ICache buffering
2015-12-02 17:18:39 -08:00
Howard Mao
cdc476a370
change Rocc parameterization
2015-12-01 17:56:09 -08:00
Andrew Waterman
e0d849fec5
Fix zscale testing
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Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
Howard Mao
c8c68e75bb
base NGenerators on NTiles, not the other way around
2015-12-01 15:26:09 -08:00
Howard Mao
40d68406d6
use xlen parameter for ALU
2015-11-30 18:04:44 -08:00
Howard Mao
23f0756978
implement support for multiple RoCC accelerators
2015-11-26 12:49:04 -08:00
Andrew Waterman
e25a020e60
Construct device tree ROM in MMIO region
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Rebuild riscv-tools for this to work!
2015-11-25 21:23:37 -08:00
Howard Mao
ec6bfde9a3
fix WritebackUnit issue in uncore
2015-11-21 16:11:22 -08:00
Howard Mao
9d50f37289
fix unused set issue for multiple L2 cache banks
2015-11-20 23:26:28 -08:00
Howard Mao
ad3b7fd0e1
adjust CacheFillTest configuration
2015-11-19 10:52:14 -08:00
Howard Mao
4806f72b08
add CacheFillTest to check L2 conflict misses
2015-11-19 00:16:28 -08:00
Howard Mao
3514b6eb87
add some more useful configurations
2015-11-18 22:11:17 -08:00
Howard Mao
379d43d5f4
make MultiChannel routing more performant
2015-11-18 22:11:17 -08:00
Andrew Waterman
5195a5b891
Remove IPI network
...
This is now provided via MMIO.
2015-11-16 21:53:14 -08:00
Howard Mao
a1063bad54
fix issues with non-allocating put/get
2015-11-12 15:54:34 -08:00
Howard Mao
6ddf81090b
didn't mean to turn off GenerateCached in last commit
2015-11-11 17:39:08 -08:00
Howard Mao
11f0b3d8db
restore old L2 cache AcquireTransactor configuration
2015-11-11 17:10:58 -08:00
Howard Mao
31da692ccc
default to single tile in WithMemtest
2015-11-11 14:54:13 -08:00
Howard Mao
55581195eb
add groundtest submodule for simple memory testing
2015-11-11 14:33:02 -08:00
Howard Mao
149480411e
make sure ClientTileLinkEnqueuer uses the correct parameters
2015-11-10 16:09:19 -08:00
