Wesley W. Terpstra
06a244f9f9
diplomacy: rename {Left,Right}Star to refer to {Source,Sink}Cardinality
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
bef593c21a
diplomacy: edges now capture their Parameters
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80ed27683e
diplomacy: protect against API leakage
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1365c5f90c
diplomacy: implement DisableMonitors scope
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
a450357744
tilelink: Monitor construction method is unconditional
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Whether or not a Monitor should be placed is decided by diplomacy.
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
7a8364ef08
diplomacy: leverage new Parameters defaults
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
655a08f12e
config: support default values for Field[T] keys
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
09d8d476c5
config: require Parameters keys to be Field[T]
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This has been good practice for ages. Enforce it.
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
42f1ae27fc
Xbar: use the IdentityModule to encourage wider fanout
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
5626cdd18f
util: add the IdentityModule, useful to dedup wires
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1a87ed1193
coreplex: add externalSlaveBuffers configuration option
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
fd8a51a910
coreplex: rename externalBuffers to externalMasterBuffers
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
4911a7d44f
tilelink Bus: toAsyncSlaves now supports BufferChains
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
040f7e1d49
tilelink: add Bus.toSyncSlaves for easy BufferChain attachment
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
d5c6494f59
tilelink: Bus.toRationalSlaves can have a BufferChain
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80965e8230
tilelink Buffer: use new :=? adapter API
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1b705f62f6
diplomacy: support :=? for unknown star inference
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
6bfea86dbf
config: support p.lift(key) to optionally return a value
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
2d93262f71
RationalCrossing: use ShiftQueues
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These are faster and small don't cost much more.
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
50d5d8c1fd
ShiftQueue: added a helper object
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
3e3024c256
ShiftQueue: fix bug in !flow case
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
ed70b243bd
plic: support a configurable number of interrupt register stages
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
9b55063de6
clint: support a configurable number of interrupt register stages
2017-09-07 16:03:34 -07:00
Megan Wachs
929a924779
Merge pull request #975 from freechipsproject/async_reg
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Cleanup some register primitives
2017-09-07 13:32:54 -07:00
Megan Wachs
1320f65ae6
Merge remote-tracking branch 'origin/master' into async_reg
2017-09-07 11:27:36 -07:00
Megan Wachs
b7acb6ca3d
Merge pull request #986 from freechipsproject/jtag_vpi_reset
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jtag_vpi: add some hysteresis for waiting for init_done
2017-09-07 11:26:42 -07:00
Megan Wachs
126d56b254
synchronizers: I learn how foldRight works
2017-09-07 10:48:27 -07:00
Megan Wachs
1da6cb85ab
shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created.
2017-09-07 09:57:50 -07:00
Megan Wachs
f68390e458
jtag_vpi: Use a parameter for INIT_DELAY vs constant
2017-09-07 09:06:07 -07:00
Megan Wachs
19eabb6728
jtag_vpi: add some hysterisis for waiting for init_done
2017-09-06 18:13:04 -07:00
Megan Wachs
dcafb5fea3
Merge remote-tracking branch 'origin/master' into async_reg
2017-09-06 11:07:19 -07:00
Megan Wachs
3c4b472f66
shift regs: remove some unnecessary primitives, and add some that actually are necessary
2017-09-06 10:37:59 -07:00
Jim Lawson
f1b7666d21
Jtagresettobool - add explicit toBool cast now required on reset. ( #984 )
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Add explicit toBool cast on reset, for chisel3 compatability
2017-09-06 09:49:47 -07:00
Wesley W. Terpstra
55a0df4186
Merge pull request #982 from freechipsproject/frontbus3
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Add a FrontBus to which low-bandwidth bus masters attach
2017-09-06 02:38:55 +02:00
Megan Wachs
777f052f95
regs: Add named/initial value ShiftRegister primitives so they are all in one place
2017-09-05 17:32:53 -07:00
Wesley W. Terpstra
b1cacc56ad
SystemBus: restore correct order of FIFOFixer and Buffer
2017-09-05 16:41:39 -07:00
Wesley W. Terpstra
b74a419bfb
FrontBus: FIFOFixer should not have a buffer between it and Xbar
2017-09-05 16:27:57 -07:00
Megan Wachs
e9e46db600
sync reg: Rename the file to reflect the more generic shift registers also in the file.
2017-09-05 15:54:25 -07:00
Megan Wachs
5df23c5514
Synchronizers: remove some newlines and unncessary gen's
2017-09-05 15:17:21 -07:00
Wesley W. Terpstra
e65f49b89a
FrontBus: attach to splitter for cross-chip visibility
2017-09-05 15:03:41 -07:00
Wesley W. Terpstra
5886025b1a
sbus => pbus: 2 buffers should already be enough
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There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.
Between them is only an AtomicAutomata.
That should be enough for most designs.
2017-09-05 15:03:38 -07:00
Henry Cook
a902e15987
pbus: clarify that we are adding buffers when attaching to sbus
2017-09-05 15:03:38 -07:00
Henry Cook
8fc4d78c84
frontbus: provide fifofixer on the side of the front bus where masters connect
2017-09-05 15:03:38 -07:00
Megan Wachs
667d966410
TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming
2017-09-05 15:03:38 -07:00
Megan Wachs
94f06dc85c
pbus: turn down overkill buffering between PBus and SBus
2017-09-05 15:03:38 -07:00
Megan Wachs
c353f68dc0
buses: name dummy buffers too
2017-09-05 15:03:38 -07:00
Henry Cook
3bde9506c6
coreplex: allow buffer chains on certain bus ports
2017-09-05 15:03:36 -07:00
Megan Wachs
57d0360c35
frontbus: Name the connection.
2017-08-30 18:07:34 -07:00
Megan Wachs
c99afe4c66
buses: Name all the things.
2017-08-30 17:31:42 -07:00
Henry Cook
32cb358c81
coreplex: include optional tile name for downstream name stabilization
2017-08-30 15:48:55 -07:00
