2012-02-26 02:09:26 +01:00
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package rocket
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2011-10-26 08:02:47 +02:00
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import Chisel._
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2012-10-08 05:15:54 +02:00
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import Node._
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2011-10-26 08:02:47 +02:00
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import Constants._
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import Instructions._
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2012-11-16 11:39:33 +01:00
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import Util._
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2012-02-09 06:43:45 +01:00
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import hwacha._
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2011-10-26 08:02:47 +02:00
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2012-11-06 08:52:32 +01:00
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class Datapath(implicit conf: RocketConfiguration) extends Component
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2011-10-26 08:02:47 +02:00
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{
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2012-11-06 08:52:32 +01:00
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val io = new Bundle {
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2013-01-07 22:38:59 +01:00
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val host = new HTIFIO(conf.lnConf.nTiles)
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val ctrl = (new CtrlDpathIO).flip
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val dmem = new HellaCacheIO()(conf.dcache)
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val ptw = (new DatapathPTWIO).flip
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val imem = new CPUFrontendIO()(conf.icache)
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val fpu = new DpathFPUIO
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val vec_ctrl = (new CtrlDpathVecIO).flip
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val vec_iface = new DpathVecInterfaceIO
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2012-11-06 08:52:32 +01:00
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}
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2011-10-26 08:02:47 +02:00
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// execute definitions
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2012-01-02 01:09:40 +01:00
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val ex_reg_pc = Reg() { UFix() };
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2012-02-09 10:28:16 +01:00
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val ex_reg_inst = Reg() { Bits() };
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2012-01-02 01:09:40 +01:00
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val ex_reg_waddr = Reg() { UFix() };
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val ex_reg_ctrl_fn_dw = Reg() { UFix() };
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val ex_reg_ctrl_fn_alu = Reg() { UFix() };
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2012-11-17 15:48:44 +01:00
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val ex_reg_sel_alu2 = Reg() { UFix() };
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2012-01-02 01:09:40 +01:00
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val ex_reg_ctrl_sel_wb = Reg() { UFix() };
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2012-11-17 15:48:44 +01:00
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val ex_reg_kill = Reg{Bool()}
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val ex_reg_rs1_bypass = Reg{Bool()}
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val ex_reg_rs1_lsb = Reg{Bits()}
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val ex_reg_rs1_msb = Reg{Bits()}
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val ex_reg_rs2_bypass = Reg{Bool()}
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val ex_reg_rs2_lsb = Reg{Bits()}
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val ex_reg_rs2_msb = Reg{Bits()}
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2011-11-02 01:59:27 +01:00
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2011-11-02 03:05:27 +01:00
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// memory definitions
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2012-01-02 01:09:40 +01:00
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val mem_reg_pc = Reg() { UFix() };
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2012-02-09 10:28:16 +01:00
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val mem_reg_inst = Reg() { Bits() };
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2012-01-02 01:09:40 +01:00
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val mem_reg_waddr = Reg() { UFix() };
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val mem_reg_wdata = Reg() { Bits() };
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2012-11-05 01:40:14 +01:00
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val mem_reg_kill = Reg() { Bool() }
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2012-11-27 05:33:41 +01:00
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val mem_reg_store_data = Reg{Bits()}
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val mem_reg_rs1 = Reg{Bits()}
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val mem_reg_rs2 = Reg{Bits()}
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2011-11-02 01:59:27 +01:00
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2011-11-02 03:05:27 +01:00
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// writeback definitions
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2012-01-03 00:42:39 +01:00
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val wb_reg_pc = Reg() { UFix() };
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2012-02-09 10:28:16 +01:00
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val wb_reg_inst = Reg() { Bits() };
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2012-02-25 21:21:10 +01:00
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val wb_reg_waddr = Reg() { UFix() }
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val wb_reg_wdata = Reg() { Bits() }
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2012-02-08 13:21:05 +01:00
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val wb_reg_ll_wb = Reg(resetVal = Bool(false));
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2012-05-24 19:33:15 +02:00
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val wb_wdata = Bits();
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2012-11-27 05:33:41 +01:00
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val wb_reg_store_data = Reg{Bits()}
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val wb_reg_rs1 = Reg{Bits()}
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val wb_reg_rs2 = Reg{Bits()}
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2012-11-17 15:48:44 +01:00
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val wb_wen = io.ctrl.wb_wen && io.ctrl.wb_valid || wb_reg_ll_wb
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2011-11-02 01:59:27 +01:00
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2011-10-26 08:02:47 +02:00
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// instruction decode stage
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2012-10-10 06:35:03 +02:00
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val id_inst = io.imem.resp.bits.data
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val id_pc = io.imem.resp.bits.pc
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2012-11-05 01:40:14 +01:00
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val regfile_ = Mem(31){Bits(width = 64)}
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2012-11-05 10:30:57 +01:00
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def readRF(a: UFix) = regfile_(~a)
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2012-11-05 01:40:14 +01:00
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def writeRF(a: UFix, d: Bits) = regfile_(~a) := d
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2011-10-26 08:02:47 +02:00
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2012-10-10 06:35:03 +02:00
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val id_raddr1 = id_inst(26,22).toUFix;
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val id_raddr2 = id_inst(21,17).toUFix;
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2011-10-26 08:02:47 +02:00
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2011-11-02 01:59:27 +01:00
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// bypass muxes
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2012-11-17 15:48:44 +01:00
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val id_rs1_zero = id_raddr1 === UFix(0)
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val id_rs1_ex_bypass = io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr
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val id_rs1_mem_bypass = io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr
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val id_rs1_bypass = id_rs1_zero || id_rs1_ex_bypass || id_rs1_mem_bypass
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val id_rs1_bypass_src = Mux(id_rs1_zero, UFix(0), Mux(id_rs1_ex_bypass, UFix(1), UFix(2) | io.ctrl.mem_load))
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2011-10-26 08:02:47 +02:00
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val id_rs1 =
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2012-11-05 10:30:57 +01:00
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Mux(id_raddr1 === UFix(0), UFix(0),
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2012-11-17 15:48:44 +01:00
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Mux(wb_wen && id_raddr1 === wb_reg_waddr, wb_wdata,
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readRF(id_raddr1)))
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val id_rs2_zero = id_raddr2 === UFix(0)
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val id_rs2_ex_bypass = io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr
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val id_rs2_mem_bypass = io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr
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val id_rs2_bypass = id_rs2_zero || id_rs2_ex_bypass || id_rs2_mem_bypass
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val id_rs2_bypass_src = Mux(id_rs2_zero, UFix(0), Mux(id_rs2_ex_bypass, UFix(1), UFix(2) | io.ctrl.mem_load))
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2012-11-05 10:30:57 +01:00
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val id_rs2 = Mux(id_raddr2 === UFix(0), UFix(0),
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2012-11-17 15:48:44 +01:00
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Mux(wb_wen && id_raddr2 === wb_reg_waddr, wb_wdata,
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readRF(id_raddr2)))
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2011-10-26 08:02:47 +02:00
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2012-02-08 15:47:26 +01:00
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// immediate generation
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2012-11-17 15:48:44 +01:00
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def imm(sel: Bits, inst: Bits) = {
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val lsbs = Mux(sel === A2_LTYPE || sel === A2_ZERO, Bits(0),
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Mux(sel === A2_BTYPE, Cat(inst(31,27), inst(16,10)),
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Mux(sel === A2_JTYPE, inst(18,7),
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inst(21,10))))
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2012-12-04 14:57:53 +01:00
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val msbs = Mux(sel === A2_ZERO, Bits(0),
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Mux(sel === A2_LTYPE, inst(26,7).toFix,
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2012-11-17 15:48:44 +01:00
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Mux(sel === A2_JTYPE, inst(31,19).toFix,
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2012-12-04 14:57:53 +01:00
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Mux(sel === A2_ITYPE, inst(21), inst(31)).toFix)))
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2012-11-17 15:48:44 +01:00
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Cat(msbs, lsbs).toFix
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}
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2012-02-08 15:47:26 +01:00
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2012-10-10 06:35:03 +02:00
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io.ctrl.inst := id_inst
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io.fpu.inst := id_inst
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2011-10-26 08:02:47 +02:00
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// execute stage
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2012-11-05 01:40:14 +01:00
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ex_reg_kill := io.ctrl.killd
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when (!io.ctrl.killd) {
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ex_reg_pc := id_pc
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ex_reg_inst := id_inst
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ex_reg_waddr := Mux(io.ctrl.sel_wa === WA_RD, id_inst(31,27).toUFix, RA)
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ex_reg_ctrl_fn_dw := io.ctrl.fn_dw.toUFix
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ex_reg_ctrl_fn_alu := io.ctrl.fn_alu
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2012-11-17 15:48:44 +01:00
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ex_reg_sel_alu2 := io.ctrl.sel_alu2
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2012-11-05 01:40:14 +01:00
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ex_reg_ctrl_sel_wb := io.ctrl.sel_wb
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2012-11-17 15:48:44 +01:00
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when (io.ctrl.ren1) {
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ex_reg_rs1_bypass := id_rs1_bypass
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ex_reg_rs1_lsb := id_rs1_bypass_src
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when (!id_rs1_bypass) {
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ex_reg_rs1_lsb := id_rs1(id_rs1_bypass_src.getWidth-1,0)
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ex_reg_rs1_msb := id_rs1(63,id_rs1_bypass_src.getWidth)
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}
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}
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when (io.ctrl.ren2) {
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ex_reg_rs2_bypass := id_rs2_bypass
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ex_reg_rs2_lsb := id_rs2_bypass_src
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when (!id_rs2_bypass) {
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ex_reg_rs2_lsb := id_rs2(id_rs2_bypass_src.getWidth-1,0)
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ex_reg_rs2_msb := id_rs2(63,id_rs2_bypass_src.getWidth)
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}
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}
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2012-11-05 01:40:14 +01:00
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}
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2011-10-26 08:02:47 +02:00
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2012-11-17 15:48:44 +01:00
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val ex_raddr1 = ex_reg_inst(26,22)
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val ex_raddr2 = ex_reg_inst(21,17)
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2012-11-16 11:39:33 +01:00
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val dmem_resp_data = if (conf.fastLoadByte) io.dmem.resp.bits.data_subword else io.dmem.resp.bits.data
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2012-11-17 15:48:44 +01:00
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val ex_rs1 =
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2012-11-25 07:01:08 +01:00
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(3) && Bool(conf.fastLoadWord), dmem_resp_data,
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2012-11-17 15:48:44 +01:00
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(2), wb_reg_wdata,
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(1), mem_reg_wdata,
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(0), Bits(0),
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Cat(ex_reg_rs1_msb, ex_reg_rs1_lsb)))))
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val ex_rs2 =
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2012-11-25 07:01:08 +01:00
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(3) && Bool(conf.fastLoadWord), dmem_resp_data,
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2012-11-17 15:48:44 +01:00
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(2), wb_reg_wdata,
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(1), mem_reg_wdata,
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(0), Bits(0),
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Cat(ex_reg_rs2_msb, ex_reg_rs2_lsb)))))
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val ex_imm = imm(ex_reg_sel_alu2, ex_reg_inst)
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val ex_op2 = Mux(ex_reg_sel_alu2 != A2_RTYPE, ex_imm, ex_rs2)
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2012-03-17 02:34:40 +01:00
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2012-11-16 11:39:33 +01:00
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val alu = new ALU
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alu.io.dw := ex_reg_ctrl_fn_dw;
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alu.io.fn := ex_reg_ctrl_fn_alu;
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alu.io.in2 := ex_op2.toUFix
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alu.io.in1 := ex_rs1.toUFix
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2011-10-26 08:02:47 +02:00
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2012-12-12 11:22:47 +01:00
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// multiplier and divider
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2013-01-06 12:47:17 +01:00
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val div = new MulDiv(mulUnroll = if (conf.fastMulDiv) 8 else 1,
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earlyOut = conf.fastMulDiv)
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2012-12-12 11:22:47 +01:00
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div.io.req.valid := io.ctrl.div_mul_val
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2012-11-18 02:24:08 +01:00
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div.io.req.bits.dw := ex_reg_ctrl_fn_dw
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div.io.req.bits.fn := ex_reg_ctrl_fn_alu
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div.io.req.bits.in1 := ex_rs1
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div.io.req.bits.in2 := ex_rs2
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div.io.req.bits.tag := ex_reg_waddr
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2012-12-12 11:22:47 +01:00
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div.io.kill := io.ctrl.div_mul_kill
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2012-11-18 02:24:08 +01:00
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div.io.resp.ready := Bool(true)
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2012-12-12 11:22:47 +01:00
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io.ctrl.div_mul_rdy := div.io.req.ready
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2011-11-02 01:59:27 +01:00
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2012-11-16 11:39:33 +01:00
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io.fpu.fromint_data := ex_rs1
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io.ctrl.ex_waddr := ex_reg_waddr
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def vaSign(a0: Bits, ea: Bits) = {
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// efficient means to compress 64-bit VA into VADDR_BITS+1 bits
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// (VA is bad if VA(VADDR_BITS) != VA(VADDR_BITS-1))
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val a = a0 >> VADDR_BITS-1
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val e = ea(VADDR_BITS,VADDR_BITS-1)
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Mux(a === UFix(0) || a === UFix(1), e != UFix(0),
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Mux(a === Fix(-1) || a === Fix(-2), e === Fix(-1),
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2012-11-20 13:06:57 +01:00
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e(0)))
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2012-11-16 11:39:33 +01:00
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}
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val ex_effective_address = Cat(vaSign(ex_rs1, alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUFix
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2011-10-26 08:02:47 +02:00
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2011-11-02 01:59:27 +01:00
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// D$ request interface (registered inside D$ module)
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// other signals (req_val, req_rdy) connect to control module
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2012-11-06 17:13:44 +01:00
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io.dmem.req.bits.addr := ex_effective_address
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2012-11-27 05:33:41 +01:00
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io.dmem.req.bits.data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_store_data)
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2012-05-02 03:23:04 +02:00
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io.dmem.req.bits.tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val)
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2012-11-06 08:52:32 +01:00
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require(io.dmem.req.bits.tag.getWidth >= 6)
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2011-10-26 08:02:47 +02:00
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2011-11-02 01:59:27 +01:00
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// processor control regfile read
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2012-11-27 10:28:06 +01:00
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val pcr = new PCR
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pcr.io.r.en := io.ctrl.pcr != PCR.N
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2012-11-17 15:48:44 +01:00
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pcr.io.r.addr := wb_reg_inst(26,22).toUFix
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2011-11-10 09:50:09 +01:00
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2012-02-20 08:15:45 +01:00
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pcr.io.host <> io.host
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2012-11-16 11:39:33 +01:00
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pcr.io <> io.ctrl
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io.ctrl.pcr_replay := pcr.io.replay
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2012-11-06 17:13:44 +01:00
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io.ptw.ptbr := pcr.io.ptbr
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io.ptw.invalidate := pcr.io.ptbr_wen
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io.ptw.status := pcr.io.status
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2011-11-02 01:59:27 +01:00
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2011-10-26 08:02:47 +02:00
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// branch resolution logic
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2012-11-25 13:24:25 +01:00
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io.ctrl.jalr_eq := ex_rs1 === id_pc.toFix && ex_reg_inst(21,10) === UFix(0)
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2012-11-16 11:39:33 +01:00
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io.ctrl.ex_br_taken :=
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Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs1 === ex_rs2,
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Mux(io.ctrl.ex_br_type === BR_NE, ex_rs1 != ex_rs2,
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Mux(io.ctrl.ex_br_type === BR_LT, ex_rs1.toFix < ex_rs2.toFix,
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Mux(io.ctrl.ex_br_type === BR_GE, ex_rs1.toFix >= ex_rs2.toFix,
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Mux(io.ctrl.ex_br_type === BR_LTU, ex_rs1 < ex_rs2,
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Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2,
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io.ctrl.ex_br_type === BR_J))))))
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2012-11-17 15:48:44 +01:00
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val ex_pc_plus4 = ex_reg_pc + 4
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val ex_branch_target = (ex_reg_pc.toFix + (ex_imm << 1)).toUFix
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2011-10-26 08:02:47 +02:00
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2012-11-17 15:48:44 +01:00
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val tsc_reg = WideCounter(64)
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|
|
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val irt_reg = WideCounter(64, io.ctrl.wb_valid)
|
2011-11-16 11:04:28 +01:00
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|
2011-10-26 08:02:47 +02:00
|
|
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// writeback select mux
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2012-11-17 15:48:44 +01:00
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val ex_wdata =
|
2012-10-12 01:50:15 +02:00
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Mux(ex_reg_ctrl_sel_wb === WB_PC, ex_pc_plus4.toFix,
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2012-11-17 15:48:44 +01:00
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Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg.value,
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|
|
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Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg.value,
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2012-11-16 11:39:33 +01:00
|
|
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alu.io.out))).toBits // WB_ALU
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2012-02-12 10:35:55 +01:00
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|
|
2011-11-02 01:59:27 +01:00
|
|
|
// memory stage
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2012-11-05 01:40:14 +01:00
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|
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mem_reg_kill := ex_reg_kill
|
|
|
|
when (!ex_reg_kill) {
|
|
|
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mem_reg_pc := ex_reg_pc
|
|
|
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mem_reg_inst := ex_reg_inst
|
|
|
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mem_reg_waddr := ex_reg_waddr
|
|
|
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mem_reg_wdata := ex_wdata
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2012-11-27 05:33:41 +01:00
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|
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mem_reg_rs1 := ex_rs1
|
|
|
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mem_reg_rs2 := ex_rs2
|
|
|
|
when (io.ctrl.ex_rs2_val) {
|
|
|
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mem_reg_store_data := StoreGen(io.ctrl.ex_mem_type, Bits(0), ex_rs2).data
|
|
|
|
}
|
2012-11-05 01:40:14 +01:00
|
|
|
}
|
2011-11-02 01:59:27 +01:00
|
|
|
|
2011-11-02 05:25:52 +01:00
|
|
|
// for load/use hazard detection (load byte/halfword)
|
|
|
|
io.ctrl.mem_waddr := mem_reg_waddr;
|
|
|
|
|
2012-02-12 13:36:01 +01:00
|
|
|
// writeback arbitration
|
2012-05-02 03:23:04 +02:00
|
|
|
val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
|
|
|
|
val dmem_resp_fpu = io.dmem.resp.bits.tag(0).toBool
|
|
|
|
val dmem_resp_waddr = io.dmem.resp.bits.tag.toUFix >> UFix(1)
|
2012-11-16 11:39:33 +01:00
|
|
|
val dmem_resp_replay = io.dmem.resp.bits.replay && dmem_resp_xpu
|
|
|
|
|
|
|
|
val mem_ll_wdata = Bits()
|
2012-12-12 11:22:47 +01:00
|
|
|
mem_ll_wdata := div.io.resp.bits.data
|
|
|
|
io.ctrl.mem_ll_waddr := div.io.resp.bits.tag
|
|
|
|
io.ctrl.mem_ll_wb := div.io.resp.valid
|
2012-11-16 11:39:33 +01:00
|
|
|
when (dmem_resp_replay) {
|
2012-11-18 02:24:08 +01:00
|
|
|
div.io.resp.ready := Bool(false)
|
2012-11-16 11:39:33 +01:00
|
|
|
mem_ll_wdata := io.dmem.resp.bits.data_subword
|
|
|
|
io.ctrl.mem_ll_waddr := dmem_resp_waddr
|
|
|
|
io.ctrl.mem_ll_wb := Bool(true)
|
|
|
|
}
|
2012-11-17 15:48:44 +01:00
|
|
|
when (io.ctrl.mem_ll_waddr === UFix(0)) { io.ctrl.mem_ll_wb := Bool(false) }
|
2011-11-02 01:59:27 +01:00
|
|
|
|
2012-05-02 03:23:04 +02:00
|
|
|
io.fpu.dmem_resp_val := io.dmem.resp.valid && dmem_resp_fpu
|
|
|
|
io.fpu.dmem_resp_data := io.dmem.resp.bits.data
|
|
|
|
io.fpu.dmem_resp_type := io.dmem.resp.bits.typ
|
2012-02-12 13:36:01 +01:00
|
|
|
io.fpu.dmem_resp_tag := dmem_resp_waddr
|
|
|
|
|
|
|
|
// writeback stage
|
2012-11-05 01:40:14 +01:00
|
|
|
when (!mem_reg_kill) {
|
|
|
|
wb_reg_pc := mem_reg_pc
|
|
|
|
wb_reg_inst := mem_reg_inst
|
|
|
|
wb_reg_waddr := mem_reg_waddr
|
|
|
|
wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata)
|
2012-11-27 05:33:41 +01:00
|
|
|
wb_reg_rs1 := mem_reg_rs1
|
|
|
|
wb_reg_rs2 := mem_reg_rs2
|
|
|
|
when (io.ctrl.mem_rs2_val) {
|
|
|
|
wb_reg_store_data := mem_reg_store_data
|
|
|
|
}
|
2012-11-05 01:40:14 +01:00
|
|
|
}
|
2012-11-16 11:39:33 +01:00
|
|
|
wb_reg_ll_wb := io.ctrl.mem_ll_wb
|
|
|
|
when (io.ctrl.mem_ll_wb) {
|
|
|
|
wb_reg_waddr := io.ctrl.mem_ll_waddr
|
2012-11-05 01:40:14 +01:00
|
|
|
wb_reg_wdata := mem_ll_wdata
|
|
|
|
}
|
2012-11-17 15:48:44 +01:00
|
|
|
wb_wdata := Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword,
|
2012-11-27 10:28:06 +01:00
|
|
|
Mux(io.ctrl.pcr != PCR.N, pcr.io.r.data,
|
2012-11-17 15:48:44 +01:00
|
|
|
wb_reg_wdata))
|
2011-11-02 01:59:27 +01:00
|
|
|
|
2012-11-18 02:24:08 +01:00
|
|
|
if (conf.vec)
|
2012-02-15 22:30:22 +01:00
|
|
|
{
|
|
|
|
// vector datapath
|
|
|
|
val vec = new rocketDpathVec()
|
|
|
|
|
|
|
|
vec.io.ctrl <> io.vec_ctrl
|
|
|
|
io.vec_iface <> vec.io.iface
|
|
|
|
|
2012-11-27 10:28:06 +01:00
|
|
|
vec.io.valid := io.ctrl.wb_valid && pcr.io.status.ev
|
2012-02-15 22:30:22 +01:00
|
|
|
vec.io.inst := wb_reg_inst
|
|
|
|
vec.io.vecbank := pcr.io.vecbank
|
|
|
|
vec.io.vecbankcnt := pcr.io.vecbankcnt
|
2012-11-17 15:48:44 +01:00
|
|
|
vec.io.wdata := wb_reg_wdata
|
2012-11-27 05:33:41 +01:00
|
|
|
vec.io.rs2 := wb_reg_store_data
|
2012-02-15 22:30:22 +01:00
|
|
|
|
2012-03-14 22:15:28 +01:00
|
|
|
pcr.io.vec_irq_aux := vec.io.irq_aux
|
2012-03-14 06:21:26 +01:00
|
|
|
pcr.io.vec_appvl := vec.io.appvl
|
|
|
|
pcr.io.vec_nxregs := vec.io.nxregs
|
|
|
|
pcr.io.vec_nfregs := vec.io.nfregs
|
|
|
|
|
2012-11-17 15:48:44 +01:00
|
|
|
when (vec.io.wen) { wb_wdata := vec.io.appvl }
|
2012-02-15 22:30:22 +01:00
|
|
|
}
|
2012-02-09 11:35:09 +01:00
|
|
|
|
2012-11-17 15:48:44 +01:00
|
|
|
when (wb_wen) { writeRF(wb_reg_waddr, wb_wdata) }
|
2012-02-25 21:21:10 +01:00
|
|
|
io.ctrl.wb_waddr := wb_reg_waddr
|
2012-02-09 10:28:16 +01:00
|
|
|
|
2011-11-02 01:59:27 +01:00
|
|
|
// scoreboard clear (for div/mul and D$ load miss writebacks)
|
2012-11-16 11:39:33 +01:00
|
|
|
io.ctrl.fp_sboard_clr := io.dmem.resp.bits.replay && dmem_resp_fpu
|
|
|
|
io.ctrl.fp_sboard_clra := dmem_resp_waddr
|
2012-04-01 07:23:51 +02:00
|
|
|
|
2011-11-02 01:59:27 +01:00
|
|
|
// processor control regfile write
|
2012-11-17 15:48:44 +01:00
|
|
|
pcr.io.w.addr := wb_reg_inst(26,22).toUFix
|
2012-11-27 10:28:06 +01:00
|
|
|
pcr.io.w.en := io.ctrl.pcr === PCR.T || io.ctrl.pcr === PCR.S || io.ctrl.pcr === PCR.C
|
|
|
|
pcr.io.w.data := Mux(io.ctrl.pcr === PCR.S, pcr.io.r.data | wb_reg_wdata,
|
|
|
|
Mux(io.ctrl.pcr === PCR.C, pcr.io.r.data & ~wb_reg_wdata,
|
2012-03-24 21:03:31 +01:00
|
|
|
wb_reg_wdata))
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2012-11-16 11:39:33 +01:00
|
|
|
// hook up I$
|
|
|
|
io.imem.req.bits.currentpc := ex_reg_pc
|
|
|
|
io.imem.req.bits.pc :=
|
|
|
|
Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
|
|
|
|
Mux(io.ctrl.sel_pc === PC_EX, Mux(io.ctrl.ex_jalr, ex_effective_address, ex_branch_target),
|
|
|
|
Mux(io.ctrl.sel_pc === PC_PCR, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec).toUFix,
|
|
|
|
wb_reg_pc))) // PC_WB
|
2012-11-17 15:48:44 +01:00
|
|
|
|
|
|
|
// expose debug signals to testbench
|
|
|
|
// XXX debug() doesn't right, so create a false dependence
|
|
|
|
val debugList = List(wb_reg_pc, wb_reg_inst, wb_wen, wb_reg_waddr, wb_wdata, wb_reg_rs1, wb_reg_rs2)
|
|
|
|
pcr.io.pc := wb_reg_pc | (debugList.map(d => d^d).reduce(_|_)).toUFix
|
|
|
|
debugList.foreach(debug _)
|
2011-10-26 08:02:47 +02:00
|
|
|
}
|