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rocket-chip/rocket/src/main/scala/tile.scala

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Scala
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package rocket
import Chisel._
import Node._
import Constants._
import uncore._
import Util._
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case class RocketConfiguration(lnConf: LogicalNetworkConfiguration, co: CoherencePolicyWithUncached,
icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, vec: Boolean,
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fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false,
fastMulDiv: Boolean = true)
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{
val dcacheReqTagBits = 9 // enforce compliance with require()
val xprlen = 64
val nxpr = 32
val nxprbits = log2Up(nxpr)
val rvc = false
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if (fastLoadByte) require(fastLoadWord)
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}
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class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) with ClientCoherenceAgent
{
val memPorts = 2 + confIn.vec
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)
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implicit val lnConf = confIn.lnConf
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implicit val conf = confIn.copy(dcache = dcConf)
val io = new Bundle {
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val tilelink = new TileLinkIO
val host = new HTIFIO(lnConf.nTiles)
}
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val core = new Core
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val icache = new Frontend()(confIn.icache)
val dcache = new HellaCache
val arbiter = new MemArbiter(memPorts)
arbiter.io.requestor(0) <> dcache.io.mem
arbiter.io.requestor(1) <> icache.io.mem
io.tilelink.xact_init <> arbiter.io.mem.xact_init
io.tilelink.xact_init_data <> dcache.io.mem.xact_init_data
arbiter.io.mem.xact_abort <> io.tilelink.xact_abort
arbiter.io.mem.xact_rep <> io.tilelink.xact_rep
io.tilelink.xact_finish <> arbiter.io.mem.xact_finish
dcache.io.mem.probe_req <> io.tilelink.probe_req
io.tilelink.probe_rep <> dcache.io.mem.probe_rep
io.tilelink.probe_rep_data <> dcache.io.mem.probe_rep_data
if (conf.vec) {
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val vicache = new Frontend()(ICacheConfig(128, 1, conf.co)) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
core.io.vimem <> vicache.io.cpu
}
core.io.host <> io.host
core.io.imem <> icache.io.cpu
core.io.dmem <> dcache.io.cpu
}