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rocket-chip/rocket/src/main/scala/tlb.scala

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// See LICENSE for license details.
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package rocket
import Chisel._
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import Util._
import junctions._
import scala.math._
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import cde.{Parameters, Field}
import uncore.PseudoLRU
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case object NTLBEntries extends Field[Int]
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trait HasTLBParameters extends HasCoreParameters {
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val entries = p(NTLBEntries)
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val camAddrBits = log2Ceil(entries)
val camTagBits = asIdBits + vpnBits
}
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abstract class TLBModule(implicit val p: Parameters) extends Module
with HasTLBParameters
abstract class TLBBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasTLBParameters
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class CAMIO(implicit p: Parameters) extends TLBBundle()(p) {
val clear = Bool(INPUT)
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val clear_mask = Bits(INPUT, entries)
val tag = Bits(INPUT, camTagBits)
val hit = Bool(OUTPUT)
val hits = UInt(OUTPUT, entries)
val valid_bits = Bits(OUTPUT, entries)
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val write = Bool(INPUT)
val write_tag = Bits(INPUT, camTagBits)
val write_addr = UInt(INPUT, camAddrBits)
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}
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class RocketCAM(implicit p: Parameters) extends TLBModule()(p) {
val io = new CAMIO
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val cam_tags = Mem(entries, Bits(width = camTagBits))
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val vb_array = Reg(init=Bits(0, entries))
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when (io.write) {
vb_array := vb_array.bitSet(io.write_addr, Bool(true))
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cam_tags(io.write_addr) := io.write_tag
}
when (io.clear) {
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vb_array := vb_array & ~io.clear_mask
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}
val hits = (0 until entries).map(i => vb_array(i) && cam_tags(i) === io.tag)
io.valid_bits := vb_array
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io.hits := Vec(hits).toBits
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io.hit := io.hits.orR
}
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class TLBReq(implicit p: Parameters) extends CoreBundle()(p) {
val asid = UInt(width = asIdBits)
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val vpn = UInt(width = vpnBitsExtended)
val passthrough = Bool()
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val instruction = Bool()
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val store = Bool()
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}
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class TLBRespNoHitIndex(implicit p: Parameters) extends CoreBundle()(p) {
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// lookup responses
val miss = Bool(OUTPUT)
val ppn = UInt(OUTPUT, ppnBits)
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val xcpt_ld = Bool(OUTPUT)
val xcpt_st = Bool(OUTPUT)
val xcpt_if = Bool(OUTPUT)
}
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class TLBResp(implicit p: Parameters) extends TLBRespNoHitIndex()(p) with HasTLBParameters {
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val hit_idx = UInt(OUTPUT, entries)
}
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class TLB(implicit p: Parameters) extends TLBModule()(p) {
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val io = new Bundle {
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val req = Decoupled(new TLBReq).flip
val resp = new TLBResp
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val ptw = new TLBPTWIO
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}
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val tag_cam = Module(new RocketCAM)
val tag_ram = Mem(entries, io.ptw.resp.bits.pte.ppn)
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val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_ready)
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val r_refill_tag = Reg(tag_cam.io.write_tag)
val r_refill_waddr = Reg(tag_cam.io.write_addr)
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val r_req = Reg(new TLBReq)
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val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
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tag_cam.io.tag := lookup_tag
tag_cam.io.write := state === s_wait && io.ptw.resp.valid
tag_cam.io.write_tag := r_refill_tag
tag_cam.io.write_addr := r_refill_waddr
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val tag_hit_addr = OHToUInt(tag_cam.io.hits)
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// permission bit arrays
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val ur_array = Reg(Vec(entries, Bool())) // user read permission
val uw_array = Reg(Vec(entries, Bool())) // user write permission
val ux_array = Reg(Vec(entries, Bool())) // user execute permission
val sr_array = Reg(Vec(entries, Bool())) // supervisor read permission
val sw_array = Reg(Vec(entries, Bool())) // supervisor write permission
val sx_array = Reg(Vec(entries, Bool())) // supervisor execute permission
val dirty_array = Reg(Vec(entries, Bool())) // PTE dirty bit
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when (io.ptw.resp.valid) {
val pte = io.ptw.resp.bits.pte
tag_ram(r_refill_waddr) := pte.ppn
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ur_array(r_refill_waddr) := pte.ur()
uw_array(r_refill_waddr) := pte.uw()
ux_array(r_refill_waddr) := pte.ux()
sr_array(r_refill_waddr) := pte.sr()
sw_array(r_refill_waddr) := pte.sw()
sx_array(r_refill_waddr) := pte.sx()
dirty_array(r_refill_waddr) := pte.d
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}
// high if there are any unused (invalid) entries in the TLB
val has_invalid_entry = !tag_cam.io.valid_bits.andR
val invalid_entry = PriorityEncoder(~tag_cam.io.valid_bits)
val plru = new PseudoLRU(entries)
val repl_waddr = Mux(has_invalid_entry, invalid_entry, plru.replace)
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val do_mprv = io.ptw.status.prv === PRV.M && io.ptw.status.mprv && !io.req.bits.instruction
val priv = Mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv)
val priv_s = priv === PRV.S
val priv_uses_vm = priv <= PRV.S
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val req_xwr = Cat(!r_req.store, r_req.store, !(r_req.instruction || r_req.store))
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val ur_bits = ur_array.toBits
val pum_ok = ~Mux(io.ptw.status.pum, ur_bits, UInt(0))
val r_array = Mux(priv_s, sr_array.toBits & pum_ok, ur_bits)
val w_array = Mux(priv_s, sw_array.toBits & pum_ok, uw_array.toBits)
val x_array = Mux(priv_s, sx_array.toBits, ux_array.toBits)
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val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
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val bad_va =
if (vpnBits == vpnBitsExtended) Bool(false)
else io.req.bits.vpn(vpnBits) =/= io.req.bits.vpn(vpnBits-1)
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// it's only a store hit if the dirty bit is set
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val tag_hits = tag_cam.io.hits & (dirty_array.toBits | ~Mux(io.req.bits.store, w_array, UInt(0)))
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val tag_hit = tag_hits.orR
val tlb_hit = vm_enabled && tag_hit
val tlb_miss = vm_enabled && !tag_hit && !bad_va
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when (io.req.valid && tlb_hit) {
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plru.access(OHToUInt(tag_cam.io.hits))
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}
val paddr = Cat(io.resp.ppn, UInt(0, pgIdxBits))
val addr_ok = addrMap.isValid(paddr)
val addr_prot = addrMap.getProt(paddr)
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io.req.ready := state === s_ready
io.resp.xcpt_ld := !addr_ok || !addr_prot.r || bad_va || tlb_hit && !(r_array & tag_cam.io.hits).orR
io.resp.xcpt_st := !addr_ok || !addr_prot.w || bad_va || tlb_hit && !(w_array & tag_cam.io.hits).orR
io.resp.xcpt_if := !addr_ok || !addr_prot.x || bad_va || tlb_hit && !(x_array & tag_cam.io.hits).orR
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io.resp.miss := tlb_miss
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io.resp.ppn := Mux(vm_enabled, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(ppnBits-1,0))
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io.resp.hit_idx := tag_cam.io.hits
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// clear entries on a TLB flush.
// TODO: selective flushing. careful with superpage mappings (flush it all)
tag_cam.io.clear := io.ptw.invalidate
tag_cam.io.clear_mask := ~UInt(0, entries)
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io.ptw.req.valid := state === s_request
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io.ptw.req.bits.addr := r_refill_tag
io.ptw.req.bits.prv := io.ptw.status.prv
io.ptw.req.bits.store := r_req.store
io.ptw.req.bits.fetch := r_req.instruction
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if (usingVM) {
when (io.req.fire() && tlb_miss) {
state := s_request
r_refill_tag := lookup_tag
r_refill_waddr := repl_waddr
r_req := io.req.bits
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}
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when (state === s_request) {
when (io.ptw.invalidate) {
state := s_ready
}
when (io.ptw.req.ready) {
state := s_wait
when (io.ptw.invalidate) { state := s_wait_invalidate }
}
}
when (state === s_wait && io.ptw.invalidate) {
state := s_wait_invalidate
}
when (io.ptw.resp.valid) {
state := s_ready
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}
}
}
class DecoupledTLB(implicit p: Parameters) extends Module {
val io = new Bundle {
val req = Decoupled(new TLBReq).flip
val resp = Decoupled(new TLBResp)
val ptw = new TLBPTWIO
}
val reqq = Queue(io.req)
val tlb = Module(new TLB)
val resp_helper = DecoupledHelper(
reqq.valid, tlb.io.req.ready, io.resp.ready)
val tlb_miss = tlb.io.resp.miss
tlb.io.req.valid := resp_helper.fire(tlb.io.req.ready)
tlb.io.req.bits := reqq.bits
reqq.ready := resp_helper.fire(reqq.valid, !tlb_miss)
io.resp.valid := resp_helper.fire(io.resp.ready, !tlb_miss)
io.resp.bits := tlb.io.resp
io.ptw <> tlb.io.ptw
}