2015-04-29 22:18:26 +02:00
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// See LICENSE for license details.
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package uncore
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import Chisel._
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2015-07-30 03:04:30 +02:00
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import junctions._
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2015-04-29 22:18:26 +02:00
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import scala.math.max
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2015-10-22 03:16:44 +02:00
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import cde.{Parameters, Field}
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2015-04-29 22:18:26 +02:00
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2015-10-14 08:42:28 +02:00
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case object TLId extends Field[String]
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case class TLKey(id: String) extends Field[TileLinkParameters]
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2015-04-29 22:18:26 +02:00
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/** Parameters exposed to the top-level design, set based on
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* external requirements or design space exploration
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2015-10-14 08:42:28 +02:00
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*
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* Coherency policy used to define custom mesage types
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* Number of manager agents
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* Number of client agents that cache data and use custom [[uncore.Acquire]] types
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* Number of client agents that do not cache data and use built-in [[uncore.Acquire]] types
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* Maximum number of unique outstanding transactions per client
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* Maximum number of clients multiplexed onto a single port
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* Maximum number of unique outstanding transactions per manager
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* Width of cache block addresses
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* Total amount of data per cache block
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* Number of data beats per cache block
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**/
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case class TileLinkParameters(
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coherencePolicy: CoherencePolicy,
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nManagers: Int,
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nCachingClients: Int,
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nCachelessClients: Int,
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maxClientXacts: Int,
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maxClientsPerPort: Int,
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maxManagerXacts: Int,
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dataBits: Int,
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dataBeats: Int = 4,
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overrideDataBitsPerBeat: Option[Int] = None
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) {
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val nClients = nCachingClients + nCachelessClients
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val writeMaskBits: Int = ((dataBits / dataBeats) - 1) / 8 + 1
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val dataBitsPerBeat: Int = overrideDataBitsPerBeat.getOrElse(dataBits / dataBeats)
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}
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2015-10-14 08:42:28 +02:00
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2015-04-29 22:18:26 +02:00
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/** Utility trait for building Modules and Bundles that use TileLink parameters */
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2015-10-06 06:41:46 +02:00
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trait HasTileLinkParameters {
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implicit val p: Parameters
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val tlExternal = p(TLKey(p(TLId)))
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val tlCoh = tlExternal.coherencePolicy
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val tlNManagers = tlExternal.nManagers
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val tlNCachingClients = tlExternal.nCachingClients
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val tlNCachelessClients = tlExternal.nCachelessClients
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val tlNClients = tlExternal.nClients
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val tlClientIdBits = log2Up(tlNClients)
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val tlManagerIdBits = log2Up(tlNManagers)
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val tlMaxClientXacts = tlExternal.maxClientXacts
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val tlMaxClientsPerPort = tlExternal.maxClientsPerPort
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val tlMaxManagerXacts = tlExternal.maxManagerXacts
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val tlClientXactIdBits = log2Up(tlMaxClientXacts*tlMaxClientsPerPort)
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val tlManagerXactIdBits = log2Up(tlMaxManagerXacts)
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2015-10-20 23:54:36 +02:00
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val tlBlockAddrBits = p(PAddrBits) - p(CacheBlockOffsetBits)
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val tlDataBeats = tlExternal.dataBeats
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val tlDataBits = tlExternal.dataBitsPerBeat
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val tlDataBytes = tlDataBits/8
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val tlWriteMaskBits = tlExternal.writeMaskBits
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val tlBeatAddrBits = log2Up(tlDataBeats)
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val tlByteAddrBits = log2Up(tlWriteMaskBits)
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val tlMemoryOpcodeBits = M_SZ
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val tlMemoryOperandSizeBits = MT_SZ
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val tlAcquireTypeBits = max(log2Up(Acquire.nBuiltInTypes),
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tlCoh.acquireTypeWidth)
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val tlAcquireUnionBits = max(tlWriteMaskBits,
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(tlByteAddrBits +
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tlMemoryOperandSizeBits +
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tlMemoryOpcodeBits)) + 1
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val tlGrantTypeBits = max(log2Up(Grant.nBuiltInTypes),
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tlCoh.grantTypeWidth) + 1
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/** Whether the underlying physical network preserved point-to-point ordering of messages */
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val tlNetworkPreservesPointToPointOrdering = false
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val tlNetworkDoesNotInterleaveBeats = true
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val amoAluOperandBits = p(AmoAluOperandBits)
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2015-11-17 04:07:58 +01:00
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val amoAluOperandBytes = amoAluOperandBits/8
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}
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abstract class TLModule(implicit val p: Parameters) extends Module
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with HasTileLinkParameters
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abstract class TLBundle(implicit val p: Parameters) extends junctions.ParameterizedBundle()(p)
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with HasTileLinkParameters
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/** Base trait for all TileLink channels */
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abstract class TileLinkChannel(implicit p: Parameters) extends TLBundle()(p) {
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def hasData(dummy: Int = 0): Bool
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def hasMultibeatData(dummy: Int = 0): Bool
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}
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/** Directionality of message channel. Used to hook up logical network ports to physical network ports */
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abstract class ClientToManagerChannel(implicit p: Parameters) extends TileLinkChannel()(p)
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/** Directionality of message channel. Used to hook up logical network ports to physical network ports */
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abstract class ManagerToClientChannel(implicit p: Parameters) extends TileLinkChannel()(p)
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/** Directionality of message channel. Used to hook up logical network ports to physical network ports */
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abstract class ClientToClientChannel(implicit p: Parameters) extends TileLinkChannel()(p) // Unused for now
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/** Common signals that are used in multiple channels.
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* These traits are useful for type parameterizing bundle wiring functions.
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*/
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/** Address of a cache block. */
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trait HasCacheBlockAddress extends HasTileLinkParameters {
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val addr_block = UInt(width = tlBlockAddrBits)
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def conflicts(that: HasCacheBlockAddress) = this.addr_block === that.addr_block
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def conflicts(addr: UInt) = this.addr_block === addr
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}
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/** Sub-block address or beat id of multi-beat data */
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trait HasTileLinkBeatId extends HasTileLinkParameters {
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val addr_beat = UInt(width = tlBeatAddrBits)
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}
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/* Client-side transaction id. Usually Miss Status Handling Register File index */
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trait HasClientTransactionId extends HasTileLinkParameters {
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val client_xact_id = Bits(width = tlClientXactIdBits)
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}
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/** Manager-side transaction id. Usually Transaction Status Handling Register File index. */
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trait HasManagerTransactionId extends HasTileLinkParameters {
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val manager_xact_id = Bits(width = tlManagerXactIdBits)
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}
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/** A single beat of cache block data */
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trait HasTileLinkData extends HasTileLinkBeatId {
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val data = UInt(width = tlDataBits)
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def hasData(dummy: Int = 0): Bool
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def hasMultibeatData(dummy: Int = 0): Bool
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}
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/** An entire cache block of data */
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trait HasTileLinkBlock extends HasTileLinkParameters {
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val data_buffer = Vec(tlDataBeats, UInt(width = tlDataBits))
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val wmask_buffer = Vec(tlDataBeats, UInt(width = tlWriteMaskBits))
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}
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/** The id of a client source or destination. Used in managers. */
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trait HasClientId extends HasTileLinkParameters {
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val client_id = UInt(width = tlClientIdBits)
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}
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2015-11-16 22:23:17 +01:00
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trait HasAcquireUnion extends HasTileLinkParameters {
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val union = Bits(width = tlAcquireUnionBits)
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// Utility funcs for accessing subblock union:
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def isBuiltInType(t: UInt): Bool
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val opCodeOff = 1
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val opSizeOff = tlMemoryOpcodeBits + opCodeOff
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val addrByteOff = tlMemoryOperandSizeBits + opSizeOff
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val addrByteMSB = tlByteAddrBits + addrByteOff
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/** Hint whether to allocate the block in any interveneing caches */
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def allocate(dummy: Int = 0) = union(0)
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/** Op code for [[uncore.PutAtomic]] operations */
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def op_code(dummy: Int = 0) = Mux(
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isBuiltInType(Acquire.putType) || isBuiltInType(Acquire.putBlockType),
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M_XWR, union(opSizeOff-1, opCodeOff))
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/** Operand size for [[uncore.PutAtomic]] */
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def op_size(dummy: Int = 0) = union(addrByteOff-1, opSizeOff)
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/** Byte address for [[uncore.PutAtomic]] operand */
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def addr_byte(dummy: Int = 0) = union(addrByteMSB-1, addrByteOff)
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2015-11-17 04:07:58 +01:00
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def amo_offset(dummy: Int = 0) = addr_byte()(tlByteAddrBits-1, log2Up(amoAluOperandBytes))
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/** Bit offset of [[uncore.PutAtomic]] operand */
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def amo_shift_bytes(dummy: Int = 0) = UInt(amoAluOperandBytes)*amo_offset()
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/** Write mask for [[uncore.Put]], [[uncore.PutBlock]], [[uncore.PutAtomic]] */
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2015-11-16 22:23:17 +01:00
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def wmask(dummy: Int = 0): UInt = {
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2016-01-13 00:32:29 +01:00
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val amo_word_mask =
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if (amoAluOperandBytes == tlWriteMaskBits) UInt(1)
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else UIntToOH(amo_offset())
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Mux(isBuiltInType(Acquire.putAtomicType),
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FillInterleaved(amoAluOperandBytes, amo_word_mask),
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Mux(isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType),
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union(tlWriteMaskBits, 1),
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UInt(0, width = tlWriteMaskBits)))
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}
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/** Full, beat-sized writemask */
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def full_wmask(dummy: Int = 0) = FillInterleaved(8, wmask())
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}
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trait HasAcquireType extends HasTileLinkParameters {
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val is_builtin_type = Bool()
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val a_type = UInt(width = tlAcquireTypeBits)
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/** Message type equality */
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def is(t: UInt) = a_type === t //TODO: make this more opaque; def ===?
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/** Is this message a built-in or custom type */
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def isBuiltInType(dummy: Int = 0): Bool = is_builtin_type
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/** Is this message a particular built-in type */
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def isBuiltInType(t: UInt): Bool = is_builtin_type && a_type === t
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/** Does this message refer to subblock operands using info in the Acquire.union subbundle */
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def isSubBlockType(dummy: Int = 0): Bool = isBuiltInType() && Acquire.typesOnSubBlocks.contains(a_type)
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/** Is this message a built-in prefetch message */
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2015-11-17 08:26:13 +01:00
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def isPrefetch(dummy: Int = 0): Bool = isBuiltInType() &&
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(is(Acquire.getPrefetchType) || is(Acquire.putPrefetchType))
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/** Does this message contain data? Assumes that no custom message types have data. */
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def hasData(dummy: Int = 0): Bool = isBuiltInType() && Acquire.typesWithData.contains(a_type)
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/** Does this message contain multiple beats of data? Assumes that no custom message types have data. */
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def hasMultibeatData(dummy: Int = 0): Bool = Bool(tlDataBeats > 1) && isBuiltInType() &&
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Acquire.typesWithMultibeatData.contains(a_type)
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/** Does this message require the manager to probe the client the very client that sent it?
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* Needed if multiple caches are attached to the same port.
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*/
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def requiresSelfProbe(dummy: Int = 0) = Bool(false)
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/** Mapping between each built-in Acquire type and a built-in Grant type. */
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def getBuiltInGrantType(dummy: Int = 0): UInt = Acquire.getBuiltInGrantType(this.a_type)
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}
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trait HasProbeType extends HasTileLinkParameters {
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val p_type = UInt(width = tlCoh.probeTypeWidth)
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def is(t: UInt) = p_type === t
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def hasData(dummy: Int = 0) = Bool(false)
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def hasMultibeatData(dummy: Int = 0) = Bool(false)
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}
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trait HasReleaseType extends HasTileLinkParameters {
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val voluntary = Bool()
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val r_type = UInt(width = tlCoh.releaseTypeWidth)
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def is(t: UInt) = r_type === t
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def hasData(dummy: Int = 0) = tlCoh.releaseTypesWithData.contains(r_type)
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def hasMultibeatData(dummy: Int = 0) = Bool(tlDataBeats > 1) &&
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tlCoh.releaseTypesWithData.contains(r_type)
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def isVoluntary(dummy: Int = 0) = voluntary
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def requiresAck(dummy: Int = 0) = !Bool(tlNetworkPreservesPointToPointOrdering)
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}
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trait HasGrantType extends HasTileLinkParameters {
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val is_builtin_type = Bool()
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val g_type = UInt(width = tlGrantTypeBits)
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// Helper funcs
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def isBuiltInType(dummy: Int = 0): Bool = is_builtin_type
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def isBuiltInType(t: UInt): Bool = is_builtin_type && g_type === t
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def is(t: UInt):Bool = g_type === t
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def hasData(dummy: Int = 0): Bool = Mux(isBuiltInType(),
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Grant.typesWithData.contains(g_type),
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tlCoh.grantTypesWithData.contains(g_type))
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def hasMultibeatData(dummy: Int = 0): Bool =
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Bool(tlDataBeats > 1) && Mux(isBuiltInType(),
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Grant.typesWithMultibeatData.contains(g_type),
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tlCoh.grantTypesWithData.contains(g_type))
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def isVoluntary(dummy: Int = 0): Bool = isBuiltInType() && (g_type === Grant.voluntaryAckType)
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def requiresAck(dummy: Int = 0): Bool = !Bool(tlNetworkPreservesPointToPointOrdering) && !isVoluntary()
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}
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/** TileLink channel bundle definitions */
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/** The Acquire channel is used to intiate coherence protocol transactions in
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* order to gain access to a cache block's data with certain permissions
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* enabled. Messages sent over this channel may be custom types defined by
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* a [[uncore.CoherencePolicy]] for cached data accesse or may be built-in types
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* used for uncached data accesses. Acquires may contain data for Put or
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* PutAtomic built-in types. After sending an Acquire, clients must
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* wait for a manager to send them a [[uncore.Grant]] message in response.
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*/
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class AcquireMetadata(implicit p: Parameters) extends ClientToManagerChannel
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with HasCacheBlockAddress
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with HasClientTransactionId
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with HasTileLinkBeatId
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with HasAcquireType
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with HasAcquireUnion {
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|
|
|
/** Complete physical address for block, beat or operand */
|
|
|
|
def full_addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, this.addr_byte())
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
|
2015-10-14 08:42:28 +02:00
|
|
|
/** [[uncore.AcquireMetadata]] with an extra field containing the data beat */
|
2015-11-16 22:23:17 +01:00
|
|
|
class Acquire(implicit p: Parameters) extends AcquireMetadata
|
|
|
|
with HasTileLinkData
|
2015-10-14 08:42:28 +02:00
|
|
|
|
|
|
|
/** [[uncore.AcquireMetadata]] with an extra field containing the entire cache block */
|
2015-11-16 22:23:17 +01:00
|
|
|
class BufferedAcquire(implicit p: Parameters) extends AcquireMetadata
|
|
|
|
with HasTileLinkBlock
|
2015-10-14 08:42:28 +02:00
|
|
|
|
2015-04-29 22:18:26 +02:00
|
|
|
/** [[uncore.Acquire]] with an extra field stating its source id */
|
2015-11-16 22:23:17 +01:00
|
|
|
class AcquireFromSrc(implicit p: Parameters) extends Acquire
|
|
|
|
with HasClientId
|
2015-04-29 22:18:26 +02:00
|
|
|
|
2015-10-14 08:42:28 +02:00
|
|
|
/** [[uncore.BufferedAcquire]] with an extra field stating its source id */
|
2015-11-16 22:23:17 +01:00
|
|
|
class BufferedAcquireFromSrc(implicit p: Parameters) extends BufferedAcquire
|
|
|
|
with HasClientId
|
|
|
|
|
|
|
|
/** Used to track metadata for transactions where multiple secondary misses have been merged
|
|
|
|
* and handled by a single transaction tracker.
|
|
|
|
*/
|
|
|
|
class SecondaryMissInfo(implicit p: Parameters) extends TLBundle
|
|
|
|
with HasClientTransactionId
|
|
|
|
with HasTileLinkBeatId
|
|
|
|
with HasClientId
|
|
|
|
with HasAcquireType
|
2015-10-14 08:42:28 +02:00
|
|
|
|
2015-04-29 22:18:26 +02:00
|
|
|
/** Contains definitions of the the built-in Acquire types and a factory
|
|
|
|
* for [[uncore.Acquire]]
|
|
|
|
*
|
|
|
|
* In general you should avoid using this factory directly and use
|
|
|
|
* [[uncore.ClientMetadata.makeAcquire]] for custom cached Acquires and
|
|
|
|
* [[uncore.Get]], [[uncore.Put]], etc. for built-in uncached Acquires.
|
|
|
|
*
|
|
|
|
* @param is_builtin_type built-in or custom type message?
|
|
|
|
* @param a_type built-in type enum or custom type enum
|
|
|
|
* @param client_xact_id client's transaction id
|
|
|
|
* @param addr_block address of the cache block
|
|
|
|
* @param addr_beat sub-block address (which beat)
|
|
|
|
* @param data data being put outwards
|
|
|
|
* @param union additional fields used for uncached types
|
|
|
|
*/
|
|
|
|
object Acquire {
|
|
|
|
val nBuiltInTypes = 5
|
|
|
|
//TODO: Use Enum
|
2015-11-17 08:26:13 +01:00
|
|
|
def getType = UInt("b000") // Get a single beat of data
|
|
|
|
def getBlockType = UInt("b001") // Get a whole block of data
|
|
|
|
def putType = UInt("b010") // Put a single beat of data
|
|
|
|
def putBlockType = UInt("b011") // Put a whole block of data
|
|
|
|
def putAtomicType = UInt("b100") // Perform an atomic memory op
|
|
|
|
def getPrefetchType = UInt("b101") // Prefetch a whole block of data
|
|
|
|
def putPrefetchType = UInt("b110") // Prefetch a whole block of data, with intent to write
|
2015-04-29 22:18:26 +02:00
|
|
|
def typesWithData = Vec(putType, putBlockType, putAtomicType)
|
|
|
|
def typesWithMultibeatData = Vec(putBlockType)
|
|
|
|
def typesOnSubBlocks = Vec(putType, getType, putAtomicType)
|
|
|
|
|
2015-11-16 22:23:17 +01:00
|
|
|
/** Mapping between each built-in Acquire type and a built-in Grant type. */
|
|
|
|
def getBuiltInGrantType(a_type: UInt): UInt = {
|
|
|
|
MuxLookup(a_type, Grant.putAckType, Array(
|
|
|
|
Acquire.getType -> Grant.getDataBeatType,
|
|
|
|
Acquire.getBlockType -> Grant.getDataBlockType,
|
|
|
|
Acquire.putType -> Grant.putAckType,
|
|
|
|
Acquire.putBlockType -> Grant.putAckType,
|
|
|
|
Acquire.putAtomicType -> Grant.getDataBeatType,
|
2015-11-17 08:26:13 +01:00
|
|
|
Acquire.getPrefetchType -> Grant.prefetchAckType,
|
|
|
|
Acquire.putPrefetchType -> Grant.prefetchAckType))
|
2015-11-16 22:23:17 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
def makeUnion(
|
|
|
|
a_type: UInt,
|
|
|
|
addr_byte: UInt,
|
|
|
|
operand_size: UInt,
|
|
|
|
opcode: UInt,
|
|
|
|
wmask: UInt,
|
|
|
|
alloc: Bool): UInt = {
|
|
|
|
MuxLookup(a_type, UInt(0), Array(
|
|
|
|
Acquire.getType -> Cat(addr_byte, operand_size, opcode, alloc),
|
|
|
|
Acquire.getBlockType -> Cat(operand_size, opcode, alloc),
|
|
|
|
Acquire.putType -> Cat(wmask, alloc),
|
|
|
|
Acquire.putBlockType -> Cat(wmask, alloc),
|
|
|
|
Acquire.putAtomicType -> Cat(addr_byte, operand_size, opcode, alloc),
|
2015-11-17 08:26:13 +01:00
|
|
|
Acquire.getPrefetchType -> Cat(M_XRD, alloc),
|
|
|
|
Acquire.putPrefetchType -> Cat(M_XWR, alloc)))
|
2015-11-16 22:23:17 +01:00
|
|
|
}
|
|
|
|
|
2015-10-14 08:42:28 +02:00
|
|
|
def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLKey(p(TLId))).writeMaskBits).toUInt
|
2015-04-29 22:18:26 +02:00
|
|
|
|
|
|
|
// Most generic constructor
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
is_builtin_type: Bool,
|
|
|
|
a_type: Bits,
|
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt,
|
|
|
|
addr_beat: UInt = UInt(0),
|
|
|
|
data: UInt = UInt(0),
|
|
|
|
union: UInt = UInt(0))
|
|
|
|
(implicit p: Parameters): Acquire = {
|
2015-07-16 05:24:03 +02:00
|
|
|
val acq = Wire(new Acquire)
|
2015-04-29 22:18:26 +02:00
|
|
|
acq.is_builtin_type := is_builtin_type
|
|
|
|
acq.a_type := a_type
|
|
|
|
acq.client_xact_id := client_xact_id
|
|
|
|
acq.addr_block := addr_block
|
|
|
|
acq.addr_beat := addr_beat
|
|
|
|
acq.data := data
|
|
|
|
acq.union := union
|
|
|
|
acq
|
|
|
|
}
|
2015-11-16 22:23:17 +01:00
|
|
|
|
2015-04-29 22:18:26 +02:00
|
|
|
// Copy constructor
|
|
|
|
def apply(a: Acquire): Acquire = {
|
2015-10-06 06:41:46 +02:00
|
|
|
val acq = Wire(new Acquire()(a.p))
|
2015-04-29 22:18:26 +02:00
|
|
|
acq := a
|
|
|
|
acq
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-11-16 22:23:17 +01:00
|
|
|
object BuiltInAcquireBuilder {
|
|
|
|
def apply(
|
|
|
|
a_type: UInt,
|
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt,
|
|
|
|
addr_beat: UInt = UInt(0),
|
|
|
|
data: UInt = UInt(0),
|
|
|
|
addr_byte: UInt = UInt(0),
|
|
|
|
operand_size: UInt = MT_Q,
|
|
|
|
opcode: UInt = UInt(0),
|
|
|
|
wmask: UInt = UInt(0),
|
|
|
|
alloc: Bool = Bool(true))
|
|
|
|
(implicit p: Parameters): Acquire = {
|
|
|
|
Acquire(
|
|
|
|
is_builtin_type = Bool(true),
|
|
|
|
a_type = a_type,
|
|
|
|
client_xact_id = client_xact_id,
|
|
|
|
addr_block = addr_block,
|
|
|
|
addr_beat = addr_beat,
|
|
|
|
data = data,
|
|
|
|
union = Acquire.makeUnion(a_type, addr_byte, operand_size, opcode, wmask, alloc))
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-29 22:18:26 +02:00
|
|
|
/** Get a single beat of data from the outer memory hierarchy
|
|
|
|
*
|
|
|
|
* The client can hint whether he block containing this beat should be
|
|
|
|
* allocated in the intervening levels of the hierarchy.
|
|
|
|
*
|
|
|
|
* @param client_xact_id client's transaction id
|
|
|
|
* @param addr_block address of the cache block
|
|
|
|
* @param addr_beat sub-block address (which beat)
|
2015-05-14 08:28:18 +02:00
|
|
|
* @param addr_byte sub-block address (which byte)
|
|
|
|
* @param operand_size {byte, half, word, double} from [[uncore.MemoryOpConstants]]
|
2015-04-29 22:18:26 +02:00
|
|
|
* @param alloc hint whether the block should be allocated in intervening caches
|
|
|
|
*/
|
|
|
|
object Get {
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt,
|
|
|
|
addr_beat: UInt,
|
|
|
|
alloc: Bool = Bool(true))
|
|
|
|
(implicit p: Parameters): Acquire = {
|
2015-11-16 22:23:17 +01:00
|
|
|
BuiltInAcquireBuilder(
|
2015-04-29 22:18:26 +02:00
|
|
|
a_type = Acquire.getType,
|
|
|
|
client_xact_id = client_xact_id,
|
|
|
|
addr_block = addr_block,
|
|
|
|
addr_beat = addr_beat,
|
2015-11-16 22:23:17 +01:00
|
|
|
opcode = M_XRD,
|
|
|
|
alloc = alloc)
|
2015-05-14 08:28:18 +02:00
|
|
|
}
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt,
|
|
|
|
addr_beat: UInt,
|
|
|
|
addr_byte: UInt,
|
|
|
|
operand_size: UInt,
|
|
|
|
alloc: Bool)
|
|
|
|
(implicit p: Parameters): Acquire = {
|
2015-11-16 22:23:17 +01:00
|
|
|
BuiltInAcquireBuilder(
|
2015-05-14 08:28:18 +02:00
|
|
|
a_type = Acquire.getType,
|
|
|
|
client_xact_id = client_xact_id,
|
|
|
|
addr_block = addr_block,
|
|
|
|
addr_beat = addr_beat,
|
2015-11-16 22:23:17 +01:00
|
|
|
addr_byte = addr_byte,
|
|
|
|
operand_size = operand_size,
|
|
|
|
opcode = M_XRD,
|
|
|
|
alloc = alloc)
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Get a whole cache block of data from the outer memory hierarchy
|
|
|
|
*
|
|
|
|
* The client can hint whether the block should be allocated in the
|
|
|
|
* intervening levels of the hierarchy.
|
|
|
|
*
|
|
|
|
* @param client_xact_id client's transaction id
|
|
|
|
* @param addr_block address of the cache block
|
|
|
|
* @param alloc hint whether the block should be allocated in intervening caches
|
|
|
|
*/
|
|
|
|
object GetBlock {
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
client_xact_id: UInt = UInt(0),
|
|
|
|
addr_block: UInt,
|
|
|
|
alloc: Bool = Bool(true))
|
|
|
|
(implicit p: Parameters): Acquire = {
|
2015-11-16 22:23:17 +01:00
|
|
|
BuiltInAcquireBuilder(
|
2015-04-29 22:18:26 +02:00
|
|
|
a_type = Acquire.getBlockType,
|
|
|
|
client_xact_id = client_xact_id,
|
|
|
|
addr_block = addr_block,
|
2015-11-16 22:23:17 +01:00
|
|
|
opcode = M_XRD,
|
|
|
|
alloc = alloc)
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Prefetch a cache block into the next-outermost level of the memory hierarchy
|
|
|
|
* with read permissions.
|
|
|
|
*
|
|
|
|
* @param client_xact_id client's transaction id
|
|
|
|
* @param addr_block address of the cache block
|
|
|
|
*/
|
|
|
|
object GetPrefetch {
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt)
|
|
|
|
(implicit p: Parameters): Acquire = {
|
2015-11-16 22:23:17 +01:00
|
|
|
BuiltInAcquireBuilder(
|
2015-11-17 08:26:13 +01:00
|
|
|
a_type = Acquire.getPrefetchType,
|
2015-04-29 22:18:26 +02:00
|
|
|
client_xact_id = client_xact_id,
|
2015-11-17 08:26:13 +01:00
|
|
|
addr_block = addr_block)
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Put a single beat of data into the outer memory hierarchy
|
|
|
|
*
|
|
|
|
* The block will be allocated in the next-outermost level of the hierarchy.
|
|
|
|
*
|
|
|
|
* @param client_xact_id client's transaction id
|
|
|
|
* @param addr_block address of the cache block
|
|
|
|
* @param addr_beat sub-block address (which beat)
|
|
|
|
* @param data data being refilled to the original requestor
|
|
|
|
* @param wmask per-byte write mask for this beat
|
2015-11-12 20:39:59 +01:00
|
|
|
* @param alloc hint whether the block should be allocated in intervening caches
|
2015-04-29 22:18:26 +02:00
|
|
|
*/
|
|
|
|
object Put {
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt,
|
|
|
|
addr_beat: UInt,
|
|
|
|
data: UInt,
|
2015-11-12 20:39:59 +01:00
|
|
|
wmask: Option[UInt]= None,
|
|
|
|
alloc: Bool = Bool(true))
|
2015-10-06 06:41:46 +02:00
|
|
|
(implicit p: Parameters): Acquire = {
|
2015-11-16 22:23:17 +01:00
|
|
|
BuiltInAcquireBuilder(
|
2015-04-29 22:18:26 +02:00
|
|
|
a_type = Acquire.putType,
|
|
|
|
addr_block = addr_block,
|
|
|
|
addr_beat = addr_beat,
|
|
|
|
client_xact_id = client_xact_id,
|
|
|
|
data = data,
|
2015-11-16 22:23:17 +01:00
|
|
|
wmask = wmask.getOrElse(Acquire.fullWriteMask),
|
|
|
|
alloc = alloc)
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Put a whole cache block of data into the outer memory hierarchy
|
|
|
|
*
|
|
|
|
* If the write mask is not full, the block will be allocated in the
|
|
|
|
* next-outermost level of the hierarchy. If the write mask is full, the
|
|
|
|
* client can hint whether the block should be allocated or not.
|
|
|
|
*
|
|
|
|
* @param client_xact_id client's transaction id
|
|
|
|
* @param addr_block address of the cache block
|
|
|
|
* @param addr_beat sub-block address (which beat of several)
|
|
|
|
* @param data data being refilled to the original requestor
|
|
|
|
* @param wmask per-byte write mask for this beat
|
|
|
|
* @param alloc hint whether the block should be allocated in intervening caches
|
|
|
|
*/
|
|
|
|
object PutBlock {
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt,
|
|
|
|
addr_beat: UInt,
|
|
|
|
data: UInt,
|
|
|
|
wmask: UInt)
|
|
|
|
(implicit p: Parameters): Acquire = {
|
2015-11-16 22:23:17 +01:00
|
|
|
BuiltInAcquireBuilder(
|
2015-04-29 22:18:26 +02:00
|
|
|
a_type = Acquire.putBlockType,
|
|
|
|
client_xact_id = client_xact_id,
|
|
|
|
addr_block = addr_block,
|
|
|
|
addr_beat = addr_beat,
|
|
|
|
data = data,
|
2015-11-16 22:23:17 +01:00
|
|
|
wmask = wmask,
|
2015-11-20 22:34:07 +01:00
|
|
|
alloc = Bool(true))
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt,
|
|
|
|
addr_beat: UInt,
|
|
|
|
data: UInt,
|
|
|
|
alloc: Bool = Bool(true))
|
|
|
|
(implicit p: Parameters): Acquire = {
|
2015-11-16 22:23:17 +01:00
|
|
|
BuiltInAcquireBuilder(
|
2015-04-29 22:18:26 +02:00
|
|
|
a_type = Acquire.putBlockType,
|
|
|
|
client_xact_id = client_xact_id,
|
|
|
|
addr_block = addr_block,
|
|
|
|
addr_beat = addr_beat,
|
|
|
|
data = data,
|
2015-11-16 22:23:17 +01:00
|
|
|
wmask = Acquire.fullWriteMask,
|
|
|
|
alloc = alloc)
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Prefetch a cache block into the next-outermost level of the memory hierarchy
|
|
|
|
* with write permissions.
|
|
|
|
*
|
|
|
|
* @param client_xact_id client's transaction id
|
|
|
|
* @param addr_block address of the cache block
|
|
|
|
*/
|
|
|
|
object PutPrefetch {
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt)
|
|
|
|
(implicit p: Parameters): Acquire = {
|
2015-11-16 22:23:17 +01:00
|
|
|
BuiltInAcquireBuilder(
|
2015-11-17 08:26:13 +01:00
|
|
|
a_type = Acquire.putPrefetchType,
|
2015-04-29 22:18:26 +02:00
|
|
|
client_xact_id = client_xact_id,
|
2015-11-17 08:26:13 +01:00
|
|
|
addr_block = addr_block)
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Perform an atomic memory operation in the next-outermost level of the memory hierarchy
|
|
|
|
*
|
|
|
|
* @param client_xact_id client's transaction id
|
|
|
|
* @param addr_block address of the cache block
|
|
|
|
* @param addr_beat sub-block address (within which beat)
|
|
|
|
* @param addr_byte sub-block address (which byte)
|
|
|
|
* @param atomic_opcode {swap, add, xor, and, min, max, minu, maxu} from [[uncore.MemoryOpConstants]]
|
|
|
|
* @param operand_size {byte, half, word, double} from [[uncore.MemoryOpConstants]]
|
|
|
|
* @param data source operand data
|
|
|
|
*/
|
|
|
|
object PutAtomic {
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt,
|
|
|
|
addr_beat: UInt,
|
|
|
|
addr_byte: UInt,
|
|
|
|
atomic_opcode: UInt,
|
|
|
|
operand_size: UInt,
|
|
|
|
data: UInt)
|
|
|
|
(implicit p: Parameters): Acquire = {
|
2015-11-16 22:23:17 +01:00
|
|
|
BuiltInAcquireBuilder(
|
2015-04-29 22:18:26 +02:00
|
|
|
a_type = Acquire.putAtomicType,
|
|
|
|
client_xact_id = client_xact_id,
|
|
|
|
addr_block = addr_block,
|
|
|
|
addr_beat = addr_beat,
|
|
|
|
data = data,
|
2015-11-16 22:23:17 +01:00
|
|
|
addr_byte = addr_byte,
|
|
|
|
operand_size = operand_size,
|
|
|
|
opcode = atomic_opcode)
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** The Probe channel is used to force clients to release data or cede permissions
|
|
|
|
* on a cache block. Clients respond to Probes with [[uncore.Release]] messages.
|
|
|
|
* The available types of Probes are customized by a particular
|
|
|
|
* [[uncore.CoherencePolicy]].
|
|
|
|
*/
|
2015-11-16 22:23:17 +01:00
|
|
|
class Probe(implicit p: Parameters) extends ManagerToClientChannel
|
|
|
|
with HasCacheBlockAddress
|
|
|
|
with HasProbeType
|
2015-04-29 22:18:26 +02:00
|
|
|
|
|
|
|
/** [[uncore.Probe]] with an extra field stating its destination id */
|
2015-10-06 06:41:46 +02:00
|
|
|
class ProbeToDst(implicit p: Parameters) extends Probe()(p) with HasClientId
|
2015-04-29 22:18:26 +02:00
|
|
|
|
|
|
|
/** Contains factories for [[uncore.Probe]] and [[uncore.ProbeToDst]]
|
|
|
|
*
|
|
|
|
* In general you should avoid using these factories directly and use
|
2015-05-07 21:35:14 +02:00
|
|
|
* [[uncore.ManagerMetadata.makeProbe(UInt,Acquire)* makeProbe]] instead.
|
2015-04-29 22:18:26 +02:00
|
|
|
*
|
|
|
|
* @param dst id of client to which probe should be sent
|
|
|
|
* @param p_type custom probe type
|
|
|
|
* @param addr_block address of the cache block
|
|
|
|
*/
|
|
|
|
object Probe {
|
2015-10-06 06:41:46 +02:00
|
|
|
def apply(p_type: UInt, addr_block: UInt)(implicit p: Parameters): Probe = {
|
2015-07-16 05:24:03 +02:00
|
|
|
val prb = Wire(new Probe)
|
2015-04-29 22:18:26 +02:00
|
|
|
prb.p_type := p_type
|
|
|
|
prb.addr_block := addr_block
|
|
|
|
prb
|
|
|
|
}
|
2015-10-06 06:41:46 +02:00
|
|
|
def apply(dst: UInt, p_type: UInt, addr_block: UInt)(implicit p: Parameters): ProbeToDst = {
|
2015-07-16 05:24:03 +02:00
|
|
|
val prb = Wire(new ProbeToDst)
|
2015-04-29 22:18:26 +02:00
|
|
|
prb.client_id := dst
|
|
|
|
prb.p_type := p_type
|
|
|
|
prb.addr_block := addr_block
|
|
|
|
prb
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** The Release channel is used to release data or permission back to the manager
|
|
|
|
* in response to [[uncore.Probe]] messages. It can also be used to voluntarily
|
|
|
|
* write back data, for example in the event that dirty data must be evicted on
|
|
|
|
* a cache miss. The available types of Release messages are always customized by
|
|
|
|
* a particular [[uncore.CoherencePolicy]]. Releases may contain data or may be
|
|
|
|
* simple acknowledgements. Voluntary Releases are acknowledged with [[uncore.Grant Grants]].
|
|
|
|
*/
|
2015-11-16 22:23:17 +01:00
|
|
|
class ReleaseMetadata(implicit p: Parameters) extends ClientToManagerChannel
|
2015-10-14 08:42:28 +02:00
|
|
|
with HasTileLinkBeatId
|
2015-04-29 22:18:26 +02:00
|
|
|
with HasCacheBlockAddress
|
2015-11-16 22:23:17 +01:00
|
|
|
with HasClientTransactionId
|
|
|
|
with HasReleaseType {
|
2015-05-20 03:40:34 +02:00
|
|
|
def full_addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, UInt(0, width = tlByteAddrBits))
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
|
2015-10-14 08:42:28 +02:00
|
|
|
/** [[uncore.ReleaseMetadata]] with an extra field containing the data beat */
|
2015-11-16 22:23:17 +01:00
|
|
|
class Release(implicit p: Parameters) extends ReleaseMetadata
|
|
|
|
with HasTileLinkData
|
2015-10-14 08:42:28 +02:00
|
|
|
|
|
|
|
/** [[uncore.ReleaseMetadata]] with an extra field containing the entire cache block */
|
2015-11-16 22:23:17 +01:00
|
|
|
class BufferedRelease(implicit p: Parameters) extends ReleaseMetadata
|
|
|
|
with HasTileLinkBlock
|
2015-10-14 08:42:28 +02:00
|
|
|
|
2015-04-29 22:18:26 +02:00
|
|
|
/** [[uncore.Release]] with an extra field stating its source id */
|
2015-11-16 22:23:17 +01:00
|
|
|
class ReleaseFromSrc(implicit p: Parameters) extends Release
|
|
|
|
with HasClientId
|
2015-04-29 22:18:26 +02:00
|
|
|
|
2015-10-14 08:42:28 +02:00
|
|
|
/** [[uncore.BufferedRelease]] with an extra field stating its source id */
|
2015-11-16 22:23:17 +01:00
|
|
|
class BufferedReleaseFromSrc(implicit p: Parameters) extends BufferedRelease
|
|
|
|
with HasClientId
|
2015-10-14 08:42:28 +02:00
|
|
|
|
2015-04-29 22:18:26 +02:00
|
|
|
/** Contains a [[uncore.Release]] factory
|
|
|
|
*
|
|
|
|
* In general you should avoid using this factory directly and use
|
|
|
|
* [[uncore.ClientMetadata.makeRelease]] instead.
|
|
|
|
*
|
|
|
|
* @param voluntary is this a voluntary writeback
|
|
|
|
* @param r_type type enum defined by coherence protocol
|
|
|
|
* @param client_xact_id client's transaction id
|
|
|
|
* @param addr_block address of the cache block
|
|
|
|
* @param addr_beat beat id of the data
|
|
|
|
* @param data data being written back
|
|
|
|
*/
|
|
|
|
object Release {
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
voluntary: Bool,
|
|
|
|
r_type: UInt,
|
|
|
|
client_xact_id: UInt,
|
|
|
|
addr_block: UInt,
|
|
|
|
addr_beat: UInt = UInt(0),
|
|
|
|
data: UInt = UInt(0))
|
|
|
|
(implicit p: Parameters): Release = {
|
2015-07-16 05:24:03 +02:00
|
|
|
val rel = Wire(new Release)
|
2015-04-29 22:18:26 +02:00
|
|
|
rel.r_type := r_type
|
|
|
|
rel.client_xact_id := client_xact_id
|
|
|
|
rel.addr_block := addr_block
|
|
|
|
rel.addr_beat := addr_beat
|
|
|
|
rel.data := data
|
|
|
|
rel.voluntary := voluntary
|
|
|
|
rel
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** The Grant channel is used to refill data or grant permissions requested of the
|
|
|
|
* manager agent via an [[uncore.Acquire]] message. It is also used to acknowledge
|
|
|
|
* the receipt of voluntary writeback from clients in the form of [[uncore.Release]]
|
|
|
|
* messages. There are built-in Grant messages used for Gets and Puts, and
|
|
|
|
* coherence policies may also define custom Grant types. Grants may contain data
|
|
|
|
* or may be simple acknowledgements. Grants are responded to with [[uncore.Finish]].
|
|
|
|
*/
|
2015-11-16 22:23:17 +01:00
|
|
|
class GrantMetadata(implicit p: Parameters) extends ManagerToClientChannel
|
2015-10-14 08:42:28 +02:00
|
|
|
with HasTileLinkBeatId
|
2015-04-29 22:18:26 +02:00
|
|
|
with HasClientTransactionId
|
2015-11-16 22:23:17 +01:00
|
|
|
with HasManagerTransactionId
|
|
|
|
with HasGrantType {
|
2015-04-29 22:18:26 +02:00
|
|
|
def makeFinish(dummy: Int = 0): Finish = {
|
2015-10-22 03:16:44 +02:00
|
|
|
val f = Wire(new Finish)
|
2015-04-29 22:18:26 +02:00
|
|
|
f.manager_xact_id := this.manager_xact_id
|
|
|
|
f
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-10-14 08:42:28 +02:00
|
|
|
/** [[uncore.GrantMetadata]] with an extra field containing a single beat of data */
|
2015-11-16 22:23:17 +01:00
|
|
|
class Grant(implicit p: Parameters) extends GrantMetadata
|
|
|
|
with HasTileLinkData
|
2015-10-14 08:42:28 +02:00
|
|
|
|
2015-04-29 22:18:26 +02:00
|
|
|
/** [[uncore.Grant]] with an extra field stating its destination */
|
2015-11-16 22:23:17 +01:00
|
|
|
class GrantToDst(implicit p: Parameters) extends Grant
|
|
|
|
with HasClientId
|
2015-04-29 22:18:26 +02:00
|
|
|
|
2015-10-14 08:42:28 +02:00
|
|
|
/** [[uncore.GrantMetadata]] with an extra field containing an entire cache block */
|
2015-11-16 22:23:17 +01:00
|
|
|
class BufferedGrant(implicit p: Parameters) extends GrantMetadata
|
|
|
|
with HasTileLinkBlock
|
2015-10-14 08:42:28 +02:00
|
|
|
|
|
|
|
/** [[uncore.BufferedGrant]] with an extra field stating its destination */
|
2015-11-16 22:23:17 +01:00
|
|
|
class BufferedGrantToDst(implicit p: Parameters) extends BufferedGrant
|
|
|
|
with HasClientId
|
2015-10-14 08:42:28 +02:00
|
|
|
|
2015-04-29 22:18:26 +02:00
|
|
|
/** Contains definitions of the the built-in grant types and factories
|
|
|
|
* for [[uncore.Grant]] and [[uncore.GrantToDst]]
|
|
|
|
*
|
|
|
|
* In general you should avoid using these factories directly and use
|
|
|
|
* [[uncore.ManagerMetadata.makeGrant(uncore.AcquireFromSrc* makeGrant]] instead.
|
|
|
|
*
|
|
|
|
* @param dst id of client to which grant should be sent
|
|
|
|
* @param is_builtin_type built-in or custom type message?
|
|
|
|
* @param g_type built-in type enum or custom type enum
|
|
|
|
* @param client_xact_id client's transaction id
|
|
|
|
* @param manager_xact_id manager's transaction id
|
|
|
|
* @param addr_beat beat id of the data
|
|
|
|
* @param data data being refilled to the original requestor
|
|
|
|
*/
|
|
|
|
object Grant {
|
|
|
|
val nBuiltInTypes = 5
|
|
|
|
def voluntaryAckType = UInt("b000") // For acking Releases
|
|
|
|
def prefetchAckType = UInt("b001") // For acking any kind of Prefetch
|
|
|
|
def putAckType = UInt("b011") // For acking any kind of non-prfetch Put
|
|
|
|
def getDataBeatType = UInt("b100") // Supplying a single beat of Get
|
|
|
|
def getDataBlockType = UInt("b101") // Supplying all beats of a GetBlock
|
|
|
|
def typesWithData = Vec(getDataBlockType, getDataBeatType)
|
|
|
|
def typesWithMultibeatData= Vec(getDataBlockType)
|
|
|
|
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
is_builtin_type: Bool,
|
|
|
|
g_type: UInt,
|
|
|
|
client_xact_id: UInt,
|
|
|
|
manager_xact_id: UInt,
|
|
|
|
addr_beat: UInt,
|
|
|
|
data: UInt)
|
|
|
|
(implicit p: Parameters): Grant = {
|
2015-09-11 02:53:04 +02:00
|
|
|
val gnt = Wire(new Grant)
|
2015-04-29 22:18:26 +02:00
|
|
|
gnt.is_builtin_type := is_builtin_type
|
|
|
|
gnt.g_type := g_type
|
|
|
|
gnt.client_xact_id := client_xact_id
|
|
|
|
gnt.manager_xact_id := manager_xact_id
|
|
|
|
gnt.addr_beat := addr_beat
|
|
|
|
gnt.data := data
|
|
|
|
gnt
|
|
|
|
}
|
|
|
|
|
|
|
|
def apply(
|
2015-10-06 06:41:46 +02:00
|
|
|
dst: UInt,
|
|
|
|
is_builtin_type: Bool,
|
|
|
|
g_type: UInt,
|
|
|
|
client_xact_id: UInt,
|
|
|
|
manager_xact_id: UInt,
|
|
|
|
addr_beat: UInt = UInt(0),
|
|
|
|
data: UInt = UInt(0))
|
|
|
|
(implicit p: Parameters): GrantToDst = {
|
2015-07-16 05:24:03 +02:00
|
|
|
val gnt = Wire(new GrantToDst)
|
2015-04-29 22:18:26 +02:00
|
|
|
gnt.client_id := dst
|
|
|
|
gnt.is_builtin_type := is_builtin_type
|
|
|
|
gnt.g_type := g_type
|
|
|
|
gnt.client_xact_id := client_xact_id
|
|
|
|
gnt.manager_xact_id := manager_xact_id
|
|
|
|
gnt.addr_beat := addr_beat
|
|
|
|
gnt.data := data
|
|
|
|
gnt
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** The Finish channel is used to provide a global ordering of transactions
|
|
|
|
* in networks that do not guarantee point-to-point ordering of messages.
|
|
|
|
* A Finsish message is sent as acknowledgement of receipt of a [[uncore.Grant]].
|
|
|
|
* When a Finish message is received, a manager knows it is safe to begin
|
|
|
|
* processing other transactions that touch the same cache block.
|
|
|
|
*/
|
2015-10-06 06:41:46 +02:00
|
|
|
class Finish(implicit p: Parameters) extends ClientToManagerChannel()(p)
|
|
|
|
with HasManagerTransactionId {
|
2015-04-29 22:18:26 +02:00
|
|
|
def hasData(dummy: Int = 0) = Bool(false)
|
|
|
|
def hasMultibeatData(dummy: Int = 0) = Bool(false)
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Complete IO definition for incoherent TileLink, including networking headers */
|
2015-10-06 06:41:46 +02:00
|
|
|
class UncachedTileLinkIO(implicit p: Parameters) extends TLBundle()(p) {
|
2015-04-29 22:18:26 +02:00
|
|
|
val acquire = new DecoupledIO(new LogicalNetworkIO(new Acquire))
|
|
|
|
val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
|
|
|
|
val finish = new DecoupledIO(new LogicalNetworkIO(new Finish))
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Complete IO definition for coherent TileLink, including networking headers */
|
2015-10-06 06:41:46 +02:00
|
|
|
class TileLinkIO(implicit p: Parameters) extends UncachedTileLinkIO()(p) {
|
2015-04-29 22:18:26 +02:00
|
|
|
val probe = new DecoupledIO(new LogicalNetworkIO(new Probe)).flip
|
|
|
|
val release = new DecoupledIO(new LogicalNetworkIO(new Release))
|
|
|
|
}
|
|
|
|
|
|
|
|
/** This version of UncachedTileLinkIO does not contain network headers.
|
|
|
|
* It is intended for use within client agents.
|
|
|
|
*
|
|
|
|
* Headers are provided in the top-level that instantiates the clients and network,
|
|
|
|
* probably using a [[uncore.ClientTileLinkNetworkPort]] module.
|
|
|
|
* By eliding the header subbundles within the clients we can enable
|
|
|
|
* hierarchical P-and-R while minimizing unconnected port errors in GDS.
|
|
|
|
*
|
|
|
|
* Secondly, this version of the interface elides [[uncore.Finish]] messages, with the
|
|
|
|
* assumption that a [[uncore.FinishUnit]] has been coupled to the TileLinkIO port
|
|
|
|
* to deal with acking received [[uncore.Grant Grants]].
|
|
|
|
*/
|
2015-10-06 06:41:46 +02:00
|
|
|
class ClientUncachedTileLinkIO(implicit p: Parameters) extends TLBundle()(p) {
|
2015-04-29 22:18:26 +02:00
|
|
|
val acquire = new DecoupledIO(new Acquire)
|
|
|
|
val grant = new DecoupledIO(new Grant).flip
|
|
|
|
}
|
|
|
|
|
|
|
|
/** This version of TileLinkIO does not contain network headers.
|
|
|
|
* It is intended for use within client agents.
|
|
|
|
*/
|
2015-10-06 06:41:46 +02:00
|
|
|
class ClientTileLinkIO(implicit p: Parameters) extends ClientUncachedTileLinkIO()(p) {
|
2015-04-29 22:18:26 +02:00
|
|
|
val probe = new DecoupledIO(new Probe).flip
|
|
|
|
val release = new DecoupledIO(new Release)
|
|
|
|
}
|
|
|
|
|
|
|
|
/** This version of TileLinkIO does not contain network headers, but
|
|
|
|
* every channel does include an extra client_id subbundle.
|
|
|
|
* It is intended for use within Management agents.
|
|
|
|
*
|
|
|
|
* Managers need to track where [[uncore.Acquire]] and [[uncore.Release]] messages
|
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|
|
* originated so that they can send a [[uncore.Grant]] to the right place.
|
|
|
|
* Similarly they must be able to issues Probes to particular clients.
|
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|
|
* However, we'd still prefer to have [[uncore.ManagerTileLinkNetworkPort]] fill in
|
|
|
|
* the header.src to enable hierarchical p-and-r of the managers. Additionally,
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|
|
* coherent clients might be mapped to random network port ids, and we'll leave it to the
|
|
|
|
* [[uncore.ManagerTileLinkNetworkPort]] to apply the correct mapping. Managers do need to
|
|
|
|
* see Finished so they know when to allow new transactions on a cache
|
|
|
|
* block to proceed.
|
|
|
|
*/
|
2015-10-06 06:41:46 +02:00
|
|
|
class ManagerTileLinkIO(implicit p: Parameters) extends TLBundle()(p) {
|
2015-04-29 22:18:26 +02:00
|
|
|
val acquire = new DecoupledIO(new AcquireFromSrc).flip
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|
|
val grant = new DecoupledIO(new GrantToDst)
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|
|
val finish = new DecoupledIO(new Finish).flip
|
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|
|
val probe = new DecoupledIO(new ProbeToDst)
|
|
|
|
val release = new DecoupledIO(new ReleaseFromSrc).flip
|
|
|
|
}
|
|
|
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|
|
|
|
/** Struct for describing per-channel queue depths */
|
|
|
|
case class TileLinkDepths(acq: Int, prb: Int, rel: Int, gnt: Int, fin: Int)
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|
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|
|
/** Optionally enqueues each [[uncore.TileLinkChannel]] individually */
|
2015-10-06 06:41:46 +02:00
|
|
|
class TileLinkEnqueuer(depths: TileLinkDepths)(implicit p: Parameters) extends Module {
|
2015-04-29 22:18:26 +02:00
|
|
|
val io = new Bundle {
|
|
|
|
val client = new TileLinkIO().flip
|
|
|
|
val manager = new TileLinkIO
|
|
|
|
}
|
|
|
|
io.manager.acquire <> (if(depths.acq > 0) Queue(io.client.acquire, depths.acq) else io.client.acquire)
|
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|
|
io.client.probe <> (if(depths.prb > 0) Queue(io.manager.probe, depths.prb) else io.manager.probe)
|
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|
|
io.manager.release <> (if(depths.rel > 0) Queue(io.client.release, depths.rel) else io.client.release)
|
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|
|
io.client.grant <> (if(depths.gnt > 0) Queue(io.manager.grant, depths.gnt) else io.manager.grant)
|
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|
|
io.manager.finish <> (if(depths.fin > 0) Queue(io.client.finish, depths.fin) else io.client.finish)
|
|
|
|
}
|
|
|
|
|
|
|
|
object TileLinkEnqueuer {
|
2015-10-06 06:41:46 +02:00
|
|
|
def apply(in: TileLinkIO, depths: TileLinkDepths)(implicit p: Parameters): TileLinkIO = {
|
|
|
|
val t = Module(new TileLinkEnqueuer(depths))
|
2015-04-29 22:18:26 +02:00
|
|
|
t.io.client <> in
|
|
|
|
t.io.manager
|
|
|
|
}
|
2015-10-06 06:41:46 +02:00
|
|
|
def apply(in: TileLinkIO, depth: Int)(implicit p: Parameters): TileLinkIO = {
|
|
|
|
apply(in, TileLinkDepths(depth, depth, depth, depth, depth))
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-11-09 20:49:19 +01:00
|
|
|
class ClientTileLinkEnqueuer(depths: TileLinkDepths)(implicit p: Parameters) extends Module {
|
|
|
|
val io = new Bundle {
|
|
|
|
val inner = new ClientTileLinkIO().flip
|
|
|
|
val outer = new ClientTileLinkIO
|
|
|
|
}
|
|
|
|
|
|
|
|
io.outer.acquire <> (if(depths.acq > 0) Queue(io.inner.acquire, depths.acq) else io.inner.acquire)
|
|
|
|
io.inner.probe <> (if(depths.prb > 0) Queue(io.outer.probe, depths.prb) else io.outer.probe)
|
|
|
|
io.outer.release <> (if(depths.rel > 0) Queue(io.inner.release, depths.rel) else io.inner.release)
|
|
|
|
io.inner.grant <> (if(depths.gnt > 0) Queue(io.outer.grant, depths.gnt) else io.outer.grant)
|
|
|
|
}
|
|
|
|
|
|
|
|
object ClientTileLinkEnqueuer {
|
|
|
|
def apply(in: ClientTileLinkIO, depths: TileLinkDepths)(implicit p: Parameters): ClientTileLinkIO = {
|
|
|
|
val t = Module(new ClientTileLinkEnqueuer(depths))
|
|
|
|
t.io.inner <> in
|
|
|
|
t.io.outer
|
|
|
|
}
|
|
|
|
def apply(in: ClientTileLinkIO, depth: Int)(implicit p: Parameters): ClientTileLinkIO = {
|
|
|
|
apply(in, TileLinkDepths(depth, depth, depth, depth, depth))
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-29 22:18:26 +02:00
|
|
|
/** Utility functions for constructing TileLinkIO arbiters */
|
2015-10-06 06:41:46 +02:00
|
|
|
trait TileLinkArbiterLike extends HasTileLinkParameters {
|
2015-04-29 22:18:26 +02:00
|
|
|
// Some shorthand type variables
|
|
|
|
type ManagerSourcedWithId = ManagerToClientChannel with HasClientTransactionId
|
|
|
|
type ClientSourcedWithId = ClientToManagerChannel with HasClientTransactionId
|
|
|
|
type ClientSourcedWithIdAndData = ClientToManagerChannel with HasClientTransactionId with HasTileLinkData
|
|
|
|
|
|
|
|
val arbN: Int // The number of ports on the client side
|
|
|
|
|
|
|
|
// These abstract funcs are filled in depending on whether the arbiter mucks with the
|
|
|
|
// outgoing client ids to track sourcing and then needs to revert them on the way back
|
|
|
|
def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int): Bits
|
|
|
|
def managerSourcedClientXactId(in: ManagerSourcedWithId): Bits
|
|
|
|
def arbIdx(in: ManagerSourcedWithId): UInt
|
|
|
|
|
|
|
|
// The following functions are all wiring helpers for each of the different types of TileLink channels
|
|
|
|
|
|
|
|
def hookupClientSource[M <: ClientSourcedWithIdAndData](
|
|
|
|
clts: Seq[DecoupledIO[LogicalNetworkIO[M]]],
|
|
|
|
mngr: DecoupledIO[LogicalNetworkIO[M]]) {
|
|
|
|
def hasData(m: LogicalNetworkIO[M]) = m.payload.hasMultibeatData()
|
2015-07-16 03:06:27 +02:00
|
|
|
val arb = Module(new LockingRRArbiter(mngr.bits, arbN, tlDataBeats, Some(hasData _)))
|
2015-04-29 22:18:26 +02:00
|
|
|
clts.zipWithIndex.zip(arb.io.in).map{ case ((req, id), arb) => {
|
|
|
|
arb.valid := req.valid
|
|
|
|
arb.bits := req.bits
|
|
|
|
arb.bits.payload.client_xact_id := clientSourcedClientXactId(req.bits.payload, id)
|
|
|
|
req.ready := arb.ready
|
|
|
|
}}
|
2015-08-02 06:09:00 +02:00
|
|
|
mngr <> arb.io.out
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
def hookupClientSourceHeaderless[M <: ClientSourcedWithIdAndData](
|
|
|
|
clts: Seq[DecoupledIO[M]],
|
|
|
|
mngr: DecoupledIO[M]) {
|
|
|
|
def hasData(m: M) = m.hasMultibeatData()
|
2015-07-16 03:06:27 +02:00
|
|
|
val arb = Module(new LockingRRArbiter(mngr.bits, arbN, tlDataBeats, Some(hasData _)))
|
2015-04-29 22:18:26 +02:00
|
|
|
clts.zipWithIndex.zip(arb.io.in).map{ case ((req, id), arb) => {
|
|
|
|
arb.valid := req.valid
|
|
|
|
arb.bits := req.bits
|
|
|
|
arb.bits.client_xact_id := clientSourcedClientXactId(req.bits, id)
|
|
|
|
req.ready := arb.ready
|
|
|
|
}}
|
2015-08-02 06:09:00 +02:00
|
|
|
mngr <> arb.io.out
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
def hookupManagerSourceWithHeader[M <: ManagerToClientChannel](
|
|
|
|
clts: Seq[DecoupledIO[LogicalNetworkIO[M]]],
|
|
|
|
mngr: DecoupledIO[LogicalNetworkIO[M]]) {
|
|
|
|
mngr.ready := Bool(false)
|
|
|
|
for (i <- 0 until arbN) {
|
|
|
|
clts(i).valid := Bool(false)
|
|
|
|
when (mngr.bits.header.dst === UInt(i)) {
|
|
|
|
clts(i).valid := mngr.valid
|
|
|
|
mngr.ready := clts(i).ready
|
|
|
|
}
|
|
|
|
clts(i).bits := mngr.bits
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
def hookupManagerSourceWithId[M <: ManagerSourcedWithId](
|
|
|
|
clts: Seq[DecoupledIO[LogicalNetworkIO[M]]],
|
|
|
|
mngr: DecoupledIO[LogicalNetworkIO[M]]) {
|
|
|
|
mngr.ready := Bool(false)
|
|
|
|
for (i <- 0 until arbN) {
|
|
|
|
clts(i).valid := Bool(false)
|
|
|
|
when (arbIdx(mngr.bits.payload) === UInt(i)) {
|
|
|
|
clts(i).valid := mngr.valid
|
|
|
|
mngr.ready := clts(i).ready
|
|
|
|
}
|
|
|
|
clts(i).bits := mngr.bits
|
|
|
|
clts(i).bits.payload.client_xact_id := managerSourcedClientXactId(mngr.bits.payload)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
def hookupManagerSourceHeaderlessWithId[M <: ManagerSourcedWithId](
|
|
|
|
clts: Seq[DecoupledIO[M]],
|
|
|
|
mngr: DecoupledIO[M]) {
|
|
|
|
mngr.ready := Bool(false)
|
|
|
|
for (i <- 0 until arbN) {
|
|
|
|
clts(i).valid := Bool(false)
|
|
|
|
when (arbIdx(mngr.bits) === UInt(i)) {
|
|
|
|
clts(i).valid := mngr.valid
|
|
|
|
mngr.ready := clts(i).ready
|
|
|
|
}
|
|
|
|
clts(i).bits := mngr.bits
|
|
|
|
clts(i).bits.client_xact_id := managerSourcedClientXactId(mngr.bits)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
def hookupManagerSourceBroadcast[M <: Data](clts: Seq[DecoupledIO[M]], mngr: DecoupledIO[M]) {
|
|
|
|
clts.map{ _.valid := mngr.valid }
|
|
|
|
clts.map{ _.bits := mngr.bits }
|
|
|
|
mngr.ready := clts.map(_.ready).reduce(_&&_)
|
|
|
|
}
|
|
|
|
|
|
|
|
def hookupFinish[M <: LogicalNetworkIO[Finish]]( clts: Seq[DecoupledIO[M]], mngr: DecoupledIO[M]) {
|
2015-07-16 03:06:27 +02:00
|
|
|
val arb = Module(new RRArbiter(mngr.bits, arbN))
|
2015-04-29 22:18:26 +02:00
|
|
|
arb.io.in <> clts
|
2015-08-02 06:09:00 +02:00
|
|
|
mngr <> arb.io.out
|
2015-04-29 22:18:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Abstract base case for any Arbiters that have UncachedTileLinkIOs */
|
2015-10-06 06:41:46 +02:00
|
|
|
abstract class UncachedTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module
|
|
|
|
with TileLinkArbiterLike {
|
2015-04-29 22:18:26 +02:00
|
|
|
val io = new Bundle {
|
2016-01-14 22:47:47 +01:00
|
|
|
val in = Vec(arbN, new UncachedTileLinkIO).flip
|
2015-04-29 22:18:26 +02:00
|
|
|
val out = new UncachedTileLinkIO
|
|
|
|
}
|
|
|
|
hookupClientSource(io.in.map(_.acquire), io.out.acquire)
|
|
|
|
hookupFinish(io.in.map(_.finish), io.out.finish)
|
|
|
|
hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Abstract base case for any Arbiters that have cached TileLinkIOs */
|
2015-10-06 06:41:46 +02:00
|
|
|
abstract class TileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module
|
|
|
|
with TileLinkArbiterLike {
|
2015-04-29 22:18:26 +02:00
|
|
|
val io = new Bundle {
|
2016-01-14 22:47:47 +01:00
|
|
|
val in = Vec(arbN, new TileLinkIO).flip
|
2015-04-29 22:18:26 +02:00
|
|
|
val out = new TileLinkIO
|
|
|
|
}
|
|
|
|
hookupClientSource(io.in.map(_.acquire), io.out.acquire)
|
|
|
|
hookupClientSource(io.in.map(_.release), io.out.release)
|
|
|
|
hookupFinish(io.in.map(_.finish), io.out.finish)
|
|
|
|
hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
|
|
|
|
hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Appends the port index of the arbiter to the client_xact_id */
|
|
|
|
trait AppendsArbiterId extends TileLinkArbiterLike {
|
|
|
|
def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) =
|
|
|
|
Cat(in.client_xact_id, UInt(id, log2Up(arbN)))
|
|
|
|
def managerSourcedClientXactId(in: ManagerSourcedWithId) =
|
2015-08-04 22:15:17 +02:00
|
|
|
in.client_xact_id >> log2Up(arbN)
|
2015-04-29 22:18:26 +02:00
|
|
|
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0).toUInt
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Uses the client_xact_id as is (assumes it has been set to port index) */
|
|
|
|
trait PassesId extends TileLinkArbiterLike {
|
|
|
|
def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) = in.client_xact_id
|
|
|
|
def managerSourcedClientXactId(in: ManagerSourcedWithId) = in.client_xact_id
|
|
|
|
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Overwrites some default client_xact_id with the port idx */
|
|
|
|
trait UsesNewId extends TileLinkArbiterLike {
|
|
|
|
def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) = UInt(id, log2Up(arbN))
|
|
|
|
def managerSourcedClientXactId(in: ManagerSourcedWithId) = UInt(0)
|
|
|
|
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id
|
|
|
|
}
|
|
|
|
|
|
|
|
// Now we can mix-in thevarious id-generation traits to make concrete arbiter classes
|
2015-10-06 06:41:46 +02:00
|
|
|
class UncachedTileLinkIOArbiterThatAppendsArbiterId(val n: Int)(implicit p: Parameters) extends UncachedTileLinkIOArbiter(n)(p) with AppendsArbiterId
|
|
|
|
class UncachedTileLinkIOArbiterThatPassesId(val n: Int)(implicit p: Parameters) extends UncachedTileLinkIOArbiter(n)(p) with PassesId
|
|
|
|
class UncachedTileLinkIOArbiterThatUsesNewId(val n: Int)(implicit p: Parameters) extends UncachedTileLinkIOArbiter(n)(p) with UsesNewId
|
|
|
|
class TileLinkIOArbiterThatAppendsArbiterId(val n: Int)(implicit p: Parameters) extends TileLinkIOArbiter(n)(p) with AppendsArbiterId
|
|
|
|
class TileLinkIOArbiterThatPassesId(val n: Int)(implicit p: Parameters) extends TileLinkIOArbiter(n)(p) with PassesId
|
|
|
|
class TileLinkIOArbiterThatUsesNewId(val n: Int)(implicit p: Parameters) extends TileLinkIOArbiter(n)(p) with UsesNewId
|
2015-04-29 22:18:26 +02:00
|
|
|
|
|
|
|
/** Concrete uncached client-side arbiter that appends the arbiter's port id to client_xact_id */
|
2015-10-06 06:41:46 +02:00
|
|
|
class ClientUncachedTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module with TileLinkArbiterLike with AppendsArbiterId {
|
2015-04-29 22:18:26 +02:00
|
|
|
val io = new Bundle {
|
2016-01-14 22:47:47 +01:00
|
|
|
val in = Vec(arbN, new ClientUncachedTileLinkIO).flip
|
2015-04-29 22:18:26 +02:00
|
|
|
val out = new ClientUncachedTileLinkIO
|
|
|
|
}
|
|
|
|
hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
|
|
|
|
hookupManagerSourceHeaderlessWithId(io.in.map(_.grant), io.out.grant)
|
|
|
|
}
|
|
|
|
|
|
|
|
/** Concrete client-side arbiter that appends the arbiter's port id to client_xact_id */
|
2015-10-06 06:41:46 +02:00
|
|
|
class ClientTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module with TileLinkArbiterLike with AppendsArbiterId {
|
2015-04-29 22:18:26 +02:00
|
|
|
val io = new Bundle {
|
2016-01-14 22:47:47 +01:00
|
|
|
val in = Vec(arbN, new ClientTileLinkIO).flip
|
2015-04-29 22:18:26 +02:00
|
|
|
val out = new ClientTileLinkIO
|
|
|
|
}
|
|
|
|
hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
|
|
|
|
hookupClientSourceHeaderless(io.in.map(_.release), io.out.release)
|
|
|
|
hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
|
|
|
|
hookupManagerSourceHeaderlessWithId(io.in.map(_.grant), io.out.grant)
|
|
|
|
}
|