2012-02-26 02:09:26 +01:00
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package rocket
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2011-10-26 08:02:47 +02:00
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2012-10-08 05:15:54 +02:00
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import Chisel._
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import Node._
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2012-10-08 22:06:45 +02:00
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import Constants._
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2012-10-02 01:08:41 +02:00
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import uncore._
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2011-10-26 08:02:47 +02:00
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2012-11-06 08:52:32 +01:00
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class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Component
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2012-10-08 22:06:45 +02:00
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{
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2012-11-06 08:52:32 +01:00
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val io = new Bundle {
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2013-01-07 22:38:59 +01:00
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val requestor = Vec(n) { new HellaCacheIO()(conf.dcache) }.flip
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val mem = new HellaCacheIO()(conf.dcache)
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2012-11-06 08:52:32 +01:00
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}
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2012-10-08 22:06:45 +02:00
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2012-11-06 17:13:44 +01:00
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val r_valid = io.requestor.map(r => Reg(r.req.valid))
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io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)
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io.requestor(0).req.ready := io.mem.req.ready
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for (i <- 1 until n)
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io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid
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io.mem.req.bits := io.requestor(n-1).req.bits
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io.mem.req.bits.tag := Cat(io.requestor(n-1).req.bits.tag, UFix(n-1, log2Up(n)))
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for (i <- n-2 to 0 by -1) {
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val req = io.requestor(i).req
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when (req.valid) {
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io.mem.req.bits.cmd := req.bits.cmd
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io.mem.req.bits.typ := req.bits.typ
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io.mem.req.bits.addr := req.bits.addr
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io.mem.req.bits.phys := req.bits.phys
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io.mem.req.bits.tag := Cat(req.bits.tag, UFix(i, log2Up(n)))
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}
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when (r_valid(i)) {
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io.mem.req.bits.kill := req.bits.kill
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io.mem.req.bits.data := req.bits.data
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}
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2012-10-08 22:06:45 +02:00
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}
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2012-11-06 17:13:44 +01:00
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for (i <- 0 until n) {
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val resp = io.requestor(i).resp
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2012-10-08 22:06:45 +02:00
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val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UFix(i)
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2012-11-06 17:13:44 +01:00
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resp.valid := io.mem.resp.valid && tag_hit
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io.requestor(i).xcpt := io.mem.xcpt
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resp.bits := io.mem.resp.bits
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resp.bits.tag := io.mem.resp.bits.tag >> UFix(log2Up(n))
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2012-11-16 11:39:33 +01:00
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resp.bits.nack := io.mem.resp.bits.nack && tag_hit
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2012-11-06 17:13:44 +01:00
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resp.bits.replay := io.mem.resp.bits.replay && tag_hit
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2012-10-08 22:06:45 +02:00
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}
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}
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2013-01-16 00:50:37 +01:00
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class UncachedRequestorIO(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val xact_init = (new ClientSourcedIO){(new LogicalNetworkIO){new TransactionInit }}
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val xact_abort = (new MasterSourcedIO) {(new LogicalNetworkIO){new TransactionAbort }}
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val xact_rep = (new MasterSourcedIO) {(new LogicalNetworkIO){new TransactionReply }}
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val xact_finish = (new ClientSourcedIO){(new LogicalNetworkIO){new TransactionFinish }}
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2012-03-06 09:31:44 +01:00
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}
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2013-01-16 00:50:37 +01:00
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class MemArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Component {
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2012-02-29 12:08:04 +01:00
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val io = new Bundle {
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2013-01-07 22:38:59 +01:00
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val mem = new UncachedRequestorIO
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val requestor = Vec(n) { new UncachedRequestorIO }.flip
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2012-02-29 12:08:04 +01:00
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}
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2011-10-26 08:02:47 +02:00
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2012-05-24 19:33:15 +02:00
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var xi_bits = new TransactionInit
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2013-01-16 00:50:37 +01:00
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xi_bits := io.requestor(n-1).xact_init.bits.payload
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xi_bits.tile_xact_id := Cat(io.requestor(n-1).xact_init.bits.payload.tile_xact_id, UFix(n-1, log2Up(n)))
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2012-03-06 09:31:44 +01:00
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for (i <- n-2 to 0 by -1)
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2012-02-29 03:59:15 +01:00
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{
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2012-05-24 19:33:15 +02:00
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var my_xi_bits = new TransactionInit
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2013-01-16 00:50:37 +01:00
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my_xi_bits := io.requestor(i).xact_init.bits.payload
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my_xi_bits.tile_xact_id := Cat(io.requestor(i).xact_init.bits.payload.tile_xact_id, UFix(i, log2Up(n)))
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2012-03-06 09:31:44 +01:00
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xi_bits = Mux(io.requestor(i).xact_init.valid, my_xi_bits, xi_bits)
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2012-02-29 03:59:15 +01:00
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}
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2013-01-16 00:50:37 +01:00
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io.mem.xact_init.bits.payload := xi_bits
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2012-11-06 17:13:44 +01:00
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io.mem.xact_init.valid := io.requestor.map(_.xact_init.valid).reduce(_||_)
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io.requestor(0).xact_init.ready := io.mem.xact_init.ready
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for (i <- 1 until n)
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io.requestor(i).xact_init.ready := io.requestor(i-1).xact_init.ready && !io.requestor(i-1).xact_init.valid
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2011-10-26 08:02:47 +02:00
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2012-03-06 09:31:44 +01:00
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var xf_bits = io.requestor(n-1).xact_finish.bits
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2012-02-29 12:08:04 +01:00
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for (i <- n-2 to 0 by -1)
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2012-03-06 09:31:44 +01:00
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xf_bits = Mux(io.requestor(i).xact_finish.valid, io.requestor(i).xact_finish.bits, xf_bits)
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2011-10-26 08:02:47 +02:00
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2012-03-06 09:31:44 +01:00
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io.mem.xact_finish.bits := xf_bits
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2012-11-06 17:13:44 +01:00
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io.mem.xact_finish.valid := io.requestor.map(_.xact_finish.valid).reduce(_||_)
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io.requestor(0).xact_finish.ready := io.mem.xact_finish.ready
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for (i <- 1 until n)
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io.requestor(i).xact_finish.ready := io.requestor(i-1).xact_finish.ready && !io.requestor(i-1).xact_finish.valid
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2012-02-29 03:59:15 +01:00
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2012-11-16 11:39:33 +01:00
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io.mem.xact_rep.ready := Bool(false)
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2012-02-20 09:51:48 +01:00
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for (i <- 0 until n)
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{
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2013-01-16 00:50:37 +01:00
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val tag = io.mem.xact_rep.bits.payload.tile_xact_id
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2012-11-16 11:39:33 +01:00
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io.requestor(i).xact_rep.valid := Bool(false)
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when (tag(log2Up(n)-1,0) === UFix(i)) {
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io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid
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io.mem.xact_rep.ready := io.requestor(i).xact_rep.ready
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}
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2012-03-06 09:31:44 +01:00
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io.requestor(i).xact_rep.bits := io.mem.xact_rep.bits
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2013-01-16 00:50:37 +01:00
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io.requestor(i).xact_rep.bits.payload.tile_xact_id := tag >> UFix(log2Up(n))
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2012-02-20 09:51:48 +01:00
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}
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2012-03-06 09:31:44 +01:00
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for (i <- 0 until n)
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{
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2013-01-16 00:50:37 +01:00
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val tag = io.mem.xact_abort.bits.payload.tile_xact_id
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2012-06-06 21:47:17 +02:00
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io.requestor(i).xact_abort.valid := io.mem.xact_abort.valid && tag(log2Up(n)-1,0) === UFix(i)
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2012-03-06 09:31:44 +01:00
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io.requestor(i).xact_abort.bits := io.mem.xact_abort.bits
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2013-01-16 00:50:37 +01:00
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io.requestor(i).xact_abort.bits.payload.tile_xact_id := tag >> UFix(log2Up(n))
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2012-03-06 09:31:44 +01:00
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}
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io.mem.xact_abort.ready := Bool(true)
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2011-10-26 08:02:47 +02:00
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}
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