2016-08-11 02:20:00 +02:00
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package coreplex
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2016-08-10 03:26:52 +02:00
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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2016-10-28 00:34:37 +02:00
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import diplomacy._
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2016-08-10 03:26:52 +02:00
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import uncore.tilelink._
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2016-10-28 00:34:37 +02:00
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import uncore.tilelink2._
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2016-08-10 03:26:52 +02:00
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import uncore.util._
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2016-09-28 06:27:07 +02:00
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import util._
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2016-08-10 03:26:52 +02:00
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import rocket._
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2016-08-10 18:49:56 +02:00
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2016-11-04 03:48:05 +01:00
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trait BroadcastL2 {
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this: CoreplexNetwork =>
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def l2ManagerFactory() = {
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2016-11-04 19:18:31 +01:00
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val bh = LazyModule(new TLBroadcast(l1tol2_lineBytes, nTrackersPerBank))
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2016-11-04 03:48:05 +01:00
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(bh.node, bh.node)
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}
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}
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/////
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2016-09-22 01:54:35 +02:00
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trait DirectConnection {
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2016-10-31 19:40:33 +01:00
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this: CoreplexNetwork with CoreplexRISCVPlatform =>
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2016-10-28 00:34:37 +02:00
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lazyTiles.map(_.slave).flatten.foreach { scratch => scratch := cbus.node }
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}
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trait DirectConnectionModule {
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2016-10-31 19:40:33 +01:00
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this: CoreplexNetworkModule with CoreplexRISCVPlatformModule =>
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2016-09-22 01:54:35 +02:00
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val tlBuffering = TileLinkDepths(1,1,2,2,0)
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val ultBuffering = UncachedTileLinkDepths(1,2)
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(tiles zip uncoreTileIOs) foreach { case (tile, uncore) =>
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2016-09-23 19:06:09 +02:00
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering) }
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2016-09-11 08:39:29 +02:00
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2016-09-22 01:54:35 +02:00
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tile.io.interrupts <> uncore.interrupts
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tile.io.hartid := uncore.hartid
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tile.io.resetVector := uncore.resetVector
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2016-09-03 02:45:08 +02:00
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}
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2016-09-22 01:54:35 +02:00
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}
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2016-09-03 02:45:08 +02:00
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2016-10-28 00:34:37 +02:00
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class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
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with DirectConnection {
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2016-10-29 12:30:49 +02:00
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override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
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2016-09-03 02:45:08 +02:00
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}
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2016-10-29 12:30:49 +02:00
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class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
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2016-09-15 21:19:22 +02:00
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2016-10-29 12:30:49 +02:00
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
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2016-10-28 00:34:37 +02:00
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with DirectConnectionModule
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2016-08-10 03:26:52 +02:00
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2016-09-22 01:54:35 +02:00
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/////
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trait AsyncConnection {
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2016-10-31 19:40:33 +01:00
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this: CoreplexNetwork with CoreplexRISCVPlatform =>
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2016-10-28 00:34:37 +02:00
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val crossings = lazyTiles.map(_.slave).map(_.map { scratch =>
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val crossing = LazyModule(new TLAsyncCrossing)
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crossing.node := cbus.node
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val monitor = (scratch := crossing.node)
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(crossing, monitor)
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})
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}
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2016-10-29 03:37:24 +02:00
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trait AsyncConnectionBundle {
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2016-10-31 19:40:33 +01:00
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this: CoreplexNetworkBundle with CoreplexRISCVPlatformBundle =>
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2016-10-29 03:37:24 +02:00
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val tcrs = Vec(nTiles, new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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})
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}
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trait AsyncConnectionModule {
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2016-10-31 19:40:33 +01:00
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this: Module with CoreplexNetworkModule with CoreplexRISCVPlatformModule {
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2016-10-29 03:37:24 +02:00
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val outer: AsyncConnection
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val io: AsyncConnectionBundle
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} =>
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2016-10-28 00:34:37 +02:00
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(outer.crossings zip io.tcrs) foreach { case (slaves, tcr) =>
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slaves.foreach { case (crossing, monitor) =>
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crossing.module.io.in_clock := clock
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crossing.module.io.in_reset := reset
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crossing.module.io.out_clock := tcr.clock
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crossing.module.io.out_reset := tcr.reset
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monitor.foreach { m =>
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m.module.clock := tcr.clock
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m.module.reset := tcr.reset
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}
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}
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}
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2016-09-22 01:54:35 +02:00
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2016-09-22 03:18:45 +02:00
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(tiles, uncoreTileIOs, io.tcrs).zipped foreach { case (tile, uncore, tcr) =>
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tile.clock := tcr.clock
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tile.reset := tcr.reset
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2016-09-22 01:54:35 +02:00
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2016-09-22 03:18:45 +02:00
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(tcr.clock, tcr.reset, t) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(tcr.clock, tcr.reset, t) }
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2016-09-22 01:54:35 +02:00
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val ti = tile.io.interrupts
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val ui = uncore.interrupts
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2016-09-22 03:18:45 +02:00
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ti.debug := LevelSyncTo(tcr.clock, ui.debug)
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ti.mtip := LevelSyncTo(tcr.clock, ui.mtip)
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ti.msip := LevelSyncTo(tcr.clock, ui.msip)
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ti.meip := LevelSyncTo(tcr.clock, ui.meip)
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ti.seip.foreach { _ := LevelSyncTo(tcr.clock, ui.seip.get) }
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2016-09-22 01:54:35 +02:00
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tile.io.hartid := uncore.hartid
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tile.io.resetVector := uncore.resetVector
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2016-08-10 03:26:52 +02:00
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}
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}
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2016-09-22 01:54:35 +02:00
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2016-10-28 00:34:37 +02:00
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class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
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with AsyncConnection {
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2016-10-29 12:30:49 +02:00
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override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this))
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2016-09-22 01:54:35 +02:00
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}
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2016-10-29 12:30:49 +02:00
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class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
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2016-10-29 03:37:24 +02:00
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with AsyncConnectionBundle
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2016-09-22 01:54:35 +02:00
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2016-10-29 12:30:49 +02:00
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class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
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2016-10-28 00:34:37 +02:00
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with AsyncConnectionModule
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