2016-11-28 01:16:37 +01:00
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// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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2014-09-13 03:06:41 +02:00
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2017-07-07 19:48:16 +02:00
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package freechips.rocketchip.rocket
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2012-10-10 06:35:03 +02:00
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2013-07-24 05:26:17 +02:00
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import Chisel._
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2016-09-29 01:10:32 +02:00
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import Chisel.ImplicitConversions._
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2017-07-07 19:48:16 +02:00
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.coreplex.CacheBlockBytes
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import freechips.rocketchip.diplomacy.RegionType
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import freechips.rocketchip.tile.{XLen, CoreModule, CoreBundle}
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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2012-10-10 06:35:03 +02:00
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2017-01-17 03:24:08 +01:00
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case object PAddrBits extends Field[Int]
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2016-08-17 05:04:02 +02:00
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case object PgLevels extends Field[Int]
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case object ASIdBits extends Field[Int]
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2015-02-02 05:04:13 +01:00
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2017-03-14 21:54:49 +01:00
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class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) {
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val rs1 = Bool()
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val rs2 = Bool()
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2017-07-06 08:53:52 +02:00
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val addr = UInt(width = vaddrBits)
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2017-03-14 21:54:49 +01:00
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val asid = UInt(width = asIdBits max 1) // TODO zero-width
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}
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2017-03-15 23:18:56 +01:00
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class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) {
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2017-03-13 04:42:51 +01:00
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val vaddr = UInt(width = vaddrBitsExtended)
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2012-11-06 17:13:44 +01:00
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val passthrough = Bool()
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2012-10-10 06:35:03 +02:00
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val instruction = Bool()
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2017-03-14 21:54:49 +01:00
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val sfence = Valid(new SFenceReq)
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2017-03-15 23:18:56 +01:00
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val size = UInt(width = log2Ceil(lgMaxSize + 1))
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2017-04-13 06:49:37 +02:00
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val cmd = Bits(width = M_SZ)
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2017-03-15 23:18:56 +01:00
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override def cloneType = new TLBReq(lgMaxSize).asInstanceOf[this.type]
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2012-10-10 06:35:03 +02:00
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}
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2017-03-27 03:18:35 +02:00
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class TLBExceptions extends Bundle {
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val ld = Bool()
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val st = Bool()
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val inst = Bool()
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}
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2016-07-02 23:26:05 +02:00
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class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
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2012-10-10 06:35:03 +02:00
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// lookup responses
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2017-03-27 03:18:35 +02:00
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val miss = Bool()
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val paddr = UInt(width = paddrBits)
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val pf = new TLBExceptions
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val ae = new TLBExceptions
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2017-04-13 06:49:37 +02:00
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val ma = new TLBExceptions
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2017-03-27 03:18:35 +02:00
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val cacheable = Bool()
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2017-08-03 02:09:38 +02:00
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val prefetchable = Bool()
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2012-10-10 06:35:03 +02:00
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}
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2017-08-08 20:52:35 +02:00
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class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
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2012-10-10 06:35:03 +02:00
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val io = new Bundle {
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2017-03-15 23:18:56 +01:00
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val req = Decoupled(new TLBReq(lgMaxSize)).flip
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2017-03-27 03:18:35 +02:00
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val resp = new TLBResp().asOutput
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2013-01-07 22:38:59 +01:00
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val ptw = new TLBPTWIO
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2012-10-10 06:35:03 +02:00
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}
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2017-03-23 03:25:02 +01:00
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class Entry extends Bundle {
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val ppn = UInt(width = ppnBits)
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val tag = UInt(width = asIdBits + vpnBits)
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val level = UInt(width = log2Ceil(pgLevels))
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val u = Bool()
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val g = Bool()
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2017-03-29 18:49:31 +02:00
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val ae = Bool()
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2017-03-23 03:25:02 +01:00
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val sw = Bool()
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val sx = Bool()
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val sr = Bool()
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2017-03-27 03:18:35 +02:00
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val pw = Bool()
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val px = Bool()
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val pr = Bool()
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2017-04-13 06:49:37 +02:00
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val pal = Bool() // AMO logical
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val paa = Bool() // AMO arithmetic
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2017-04-15 03:22:12 +02:00
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val eff = Bool() // get/put effects
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2017-03-27 03:18:35 +02:00
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val c = Bool()
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2017-03-23 03:25:02 +01:00
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}
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val totalEntries = nEntries + 1
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val normalEntries = nEntries
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val specialEntry = nEntries
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2017-06-09 02:22:51 +02:00
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val aeEntry = specialEntry - (1 << log2Floor(nEntries))
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2017-03-13 04:42:51 +01:00
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val valid = Reg(init = UInt(0, totalEntries))
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2017-03-23 03:25:02 +01:00
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val reg_entries = Reg(Vec(totalEntries, UInt(width = new Entry().getWidth)))
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val entries = reg_entries.map(_.asTypeOf(new Entry))
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2016-03-31 07:48:31 +02:00
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2013-09-10 19:51:35 +02:00
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val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(UInt(), 4)
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2013-08-16 00:28:15 +02:00
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val state = Reg(init=s_ready)
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2016-07-02 23:26:05 +02:00
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val r_refill_tag = Reg(UInt(width = asIdBits + vpnBits))
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2017-03-13 04:42:51 +01:00
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val r_refill_waddr = Reg(UInt(width = log2Ceil(normalEntries)))
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2017-03-15 23:18:56 +01:00
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val r_req = Reg(new TLBReq(lgMaxSize))
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2016-08-03 00:11:48 +02:00
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2017-08-08 20:52:35 +02:00
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val priv = if (instruction) io.ptw.status.prv else io.ptw.status.dprv
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2017-03-15 20:04:29 +01:00
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val priv_s = priv(0)
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2017-03-14 22:37:09 +01:00
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val priv_uses_vm = priv <= PRV.S
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2017-03-13 04:42:51 +01:00
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val vm_enabled = Bool(usingVM) && io.ptw.ptbr.mode(io.ptw.ptbr.mode.getWidth-1) && priv_uses_vm && !io.req.bits.passthrough
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2016-08-03 00:11:48 +02:00
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// share a single physical memory attribute checker (unshare if critical path)
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2017-03-13 04:42:51 +01:00
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val (vpn, pgOffset) = Split(io.req.bits.vaddr, pgIdxBits)
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2016-08-03 00:11:48 +02:00
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val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
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val do_refill = Bool(usingVM) && io.ptw.resp.valid
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2017-03-14 21:54:49 +01:00
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val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate)
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2017-03-21 20:01:32 +01:00
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val mpu_ppn = Mux(do_refill, refill_ppn,
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2017-04-14 00:57:57 +02:00
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Mux(vm_enabled, entries.last.ppn, vpn))
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2017-03-21 20:01:32 +01:00
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val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
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2017-03-15 23:18:56 +01:00
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val pmp = Module(new PMPChecker(lgMaxSize))
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2017-03-15 09:18:39 +01:00
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pmp.io.addr := mpu_physaddr
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2017-03-15 23:18:56 +01:00
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pmp.io.size := io.req.bits.size
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2017-03-28 02:53:48 +02:00
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pmp.io.pmp := (io.ptw.pmp: Seq[PMP])
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2017-03-24 21:01:47 +01:00
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pmp.io.prv := Mux(Bool(usingVM) && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S, priv)
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2016-11-27 00:11:42 +01:00
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val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_)
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2016-11-21 20:48:10 +01:00
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def fastCheck(member: TLManagerParameters => Boolean) =
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2017-06-01 23:59:53 +02:00
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legal_address && edge.manager.fastProperty(mpu_physaddr, member, (b:Boolean) => Bool(b))
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2017-04-13 06:49:37 +02:00
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val cacheable = fastCheck(_.supportsAcquireB)
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2017-08-03 02:09:38 +02:00
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val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits)(mpu_physaddr).homogeneous
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2017-03-16 02:00:32 +01:00
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val prot_r = fastCheck(_.supportsGet) && pmp.io.r
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val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w
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2017-04-13 06:49:37 +02:00
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val prot_al = fastCheck(_.supportsLogical) || cacheable
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val prot_aa = fastCheck(_.supportsArithmetic) || cacheable
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2017-03-16 02:00:32 +01:00
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val prot_x = fastCheck(_.executable) && pmp.io.x
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2017-04-15 03:22:12 +02:00
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val prot_eff = fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType)
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2016-11-21 20:48:10 +01:00
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2017-03-13 04:42:51 +01:00
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val lookup_tag = Cat(io.ptw.ptbr.asid, vpn(vpnBits-1,0))
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val hitsVec = (0 until totalEntries).map { i => vm_enabled && {
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var tagMatch = valid(i)
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for (j <- 0 until pgLevels) {
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val base = vpnBits - (j + 1) * pgLevelBits
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2017-03-23 03:25:02 +01:00
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tagMatch = tagMatch && (entries(i).level < j || entries(i).tag(base + pgLevelBits - 1, base) === vpn(base + pgLevelBits - 1, base))
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2017-03-13 04:42:51 +01:00
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}
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tagMatch
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}} :+ !vm_enabled
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2016-08-01 02:13:52 +02:00
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val hits = hitsVec.asUInt
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2017-03-23 03:25:02 +01:00
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val level = Mux1H(hitsVec.init, entries.map(_.level))
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val partialPPN = Mux1H(hitsVec.init, entries.map(_.ppn))
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2017-03-13 04:42:51 +01:00
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val ppn = {
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var ppn = Mux(vm_enabled, partialPPN, vpn)(pgLevelBits*pgLevels - 1, pgLevelBits*(pgLevels - 1))
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for (i <- 1 until pgLevels)
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ppn = Cat(ppn, (Mux(level < i, vpn, 0.U) | partialPPN)(vpnBits - i*pgLevelBits - 1, vpnBits - (i + 1)*pgLevelBits))
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ppn
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}
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2017-03-20 09:34:47 +01:00
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2012-10-10 06:35:03 +02:00
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// permission bit arrays
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2017-03-14 21:54:49 +01:00
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when (do_refill && !invalidate_refill) {
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2017-06-09 02:22:51 +02:00
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val waddr = Mux(io.ptw.resp.bits.ae, aeEntry.U, Mux(!io.ptw.resp.bits.homogeneous, specialEntry.U, r_refill_waddr))
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2015-03-28 00:20:59 +01:00
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val pte = io.ptw.resp.bits.pte
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2017-03-23 03:25:02 +01:00
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val newEntry = Wire(new Entry)
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newEntry.ppn := pte.ppn
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newEntry.tag := r_refill_tag
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newEntry.level := io.ptw.resp.bits.level
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2017-03-27 03:18:35 +02:00
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newEntry.c := cacheable
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2017-03-23 03:25:02 +01:00
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newEntry.u := pte.u
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newEntry.g := pte.g
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2017-03-29 18:49:31 +02:00
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newEntry.ae := io.ptw.resp.bits.ae
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2017-06-09 02:22:51 +02:00
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newEntry.sr := pte.sr()
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newEntry.sw := pte.sw()
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newEntry.sx := pte.sx()
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2017-03-27 03:18:35 +02:00
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newEntry.pr := prot_r && !io.ptw.resp.bits.ae
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newEntry.pw := prot_w && !io.ptw.resp.bits.ae
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newEntry.px := prot_x && !io.ptw.resp.bits.ae
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2017-04-13 06:49:37 +02:00
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newEntry.pal := prot_al
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newEntry.paa := prot_aa
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2017-04-15 03:22:12 +02:00
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newEntry.eff := prot_eff
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2017-03-23 03:25:02 +01:00
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valid := valid | UIntToOH(waddr)
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reg_entries(waddr) := newEntry.asUInt
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2012-10-10 06:35:03 +02:00
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}
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2017-03-20 09:34:47 +01:00
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2017-03-13 04:42:51 +01:00
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val plru = new PseudoLRU(normalEntries)
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2017-03-20 09:34:47 +01:00
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val repl_waddr = Mux(!valid(normalEntries-1, 0).andR, PriorityEncoder(~valid(normalEntries-1, 0)), plru.replace)
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2016-03-03 08:29:58 +01:00
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2017-06-09 02:22:51 +02:00
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val ptw_ae_array = entries(aeEntry).ae << aeEntry
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val priv_rw_ok = Mux(!priv_s || io.ptw.status.sum, entries.map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries.map(_.u).asUInt, 0.U)
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val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt)
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val r_array = Cat(true.B, priv_rw_ok & (entries.map(_.sr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.sx).asUInt, UInt(0))))
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val w_array = Cat(true.B, priv_rw_ok & entries.map(_.sw).asUInt)
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val x_array = Cat(true.B, priv_x_ok & entries.map(_.sx).asUInt)
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2017-03-27 03:18:35 +02:00
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val pr_array = Cat(Fill(2, prot_r), entries.init.map(_.pr).asUInt)
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val pw_array = Cat(Fill(2, prot_w), entries.init.map(_.pw).asUInt)
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val px_array = Cat(Fill(2, prot_x), entries.init.map(_.px).asUInt)
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2017-04-13 06:49:37 +02:00
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val paa_array = Cat(Fill(2, prot_aa), entries.init.map(_.paa).asUInt)
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val pal_array = Cat(Fill(2, prot_al), entries.init.map(_.pal).asUInt)
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2017-04-15 03:22:12 +02:00
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val eff_array = Cat(Fill(2, prot_eff), entries.init.map(_.eff).asUInt)
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2017-03-27 03:18:35 +02:00
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val c_array = Cat(Fill(2, cacheable), entries.init.map(_.c).asUInt)
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2017-08-03 02:09:38 +02:00
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val prefetchable_array = Cat(cacheable && homogeneous, false.B, entries.init.map(_.c).asUInt)
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2015-03-14 10:49:07 +01:00
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2017-04-13 06:49:37 +02:00
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val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1)).orR
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2017-04-15 03:22:12 +02:00
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val bad_va = vm_enabled &&
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(if (vpnBits == vpnBitsExtended) Bool(false)
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else vpn(vpnBits) =/= vpn(vpnBits-1))
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2017-04-15 09:53:31 +02:00
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2017-04-20 01:52:23 +02:00
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val lrscAllowed = Mux(Bool(usingDataScratchpad), 0.U, c_array)
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2017-04-15 09:53:31 +02:00
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val ae_array =
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Mux(misaligned, eff_array, 0.U) |
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2017-04-20 01:52:23 +02:00
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Mux(Bool(usingAtomics) && io.req.bits.cmd.isOneOf(M_XLR, M_XSC), ~lrscAllowed, 0.U)
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2017-04-15 09:53:31 +02:00
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val ae_ld_array = Mux(isRead(io.req.bits.cmd), ae_array | ~pr_array, 0.U)
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val ae_st_array =
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Mux(isWrite(io.req.bits.cmd), ae_array | ~pw_array, 0.U) |
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Mux(Bool(usingAtomics) && isAMOLogical(io.req.bits.cmd), ~pal_array, 0.U) |
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Mux(Bool(usingAtomics) && isAMOArithmetic(io.req.bits.cmd), ~paa_array, 0.U)
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val ma_ld_array = Mux(misaligned && isRead(io.req.bits.cmd), ~eff_array, 0.U)
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val ma_st_array = Mux(misaligned && isWrite(io.req.bits.cmd), ~eff_array, 0.U)
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2017-06-09 02:22:51 +02:00
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val pf_ld_array = Mux(isRead(io.req.bits.cmd), ~(r_array | ptw_ae_array), 0.U)
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val pf_st_array = Mux(isWrite(io.req.bits.cmd), ~(w_array | ptw_ae_array), 0.U)
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val pf_inst_array = ~(x_array | ptw_ae_array)
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2017-04-15 09:53:31 +02:00
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2017-03-13 04:42:51 +01:00
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val tlb_hit = hits(totalEntries-1, 0).orR
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2017-03-14 21:54:49 +01:00
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val tlb_miss = vm_enabled && !bad_va && !tlb_hit && !io.req.bits.sfence.valid
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2017-03-13 04:42:51 +01:00
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when (io.req.valid && !tlb_miss && !hits(specialEntry)) {
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plru.access(OHToUInt(hits(normalEntries-1, 0)))
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2012-10-10 06:35:03 +02:00
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}
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2017-03-10 23:00:36 +01:00
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// Superpages create the possibility that two entries in the TLB may match.
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|
// This corresponds to a software bug, but we can't return complete garbage;
|
|
|
|
// we must return either the old translation or the new translation. This
|
|
|
|
// isn't compatible with the Mux1H approach. So, flush the TLB and report
|
|
|
|
// a miss on duplicate entries.
|
2017-03-13 04:42:51 +01:00
|
|
|
val multipleHits = PopCountAtLeast(hits(totalEntries-1, 0), 2)
|
2017-03-10 23:00:36 +01:00
|
|
|
|
2012-10-10 06:35:03 +02:00
|
|
|
io.req.ready := state === s_ready
|
2017-04-15 09:53:31 +02:00
|
|
|
io.resp.pf.ld := (bad_va && isRead(io.req.bits.cmd)) || (pf_ld_array & hits).orR
|
|
|
|
io.resp.pf.st := (bad_va && isWrite(io.req.bits.cmd)) || (pf_st_array & hits).orR
|
2017-06-09 02:22:51 +02:00
|
|
|
io.resp.pf.inst := bad_va || (pf_inst_array & hits).orR
|
2017-04-15 09:53:31 +02:00
|
|
|
io.resp.ae.ld := (ae_ld_array & hits).orR
|
|
|
|
io.resp.ae.st := (ae_st_array & hits).orR
|
2017-03-27 03:18:35 +02:00
|
|
|
io.resp.ae.inst := (~px_array & hits).orR
|
2017-04-15 09:53:31 +02:00
|
|
|
io.resp.ma.ld := (ma_ld_array & hits).orR
|
|
|
|
io.resp.ma.st := (ma_st_array & hits).orR
|
2017-04-13 06:49:37 +02:00
|
|
|
io.resp.ma.inst := false // this is up to the pipeline to figure out
|
2016-08-03 00:11:48 +02:00
|
|
|
io.resp.cacheable := (c_array & hits).orR
|
2017-08-03 02:09:38 +02:00
|
|
|
io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint)
|
2017-03-10 23:00:36 +01:00
|
|
|
io.resp.miss := do_refill || tlb_miss || multipleHits
|
2017-03-13 04:42:51 +01:00
|
|
|
io.resp.paddr := Cat(ppn, pgOffset)
|
2015-03-14 10:49:07 +01:00
|
|
|
|
2012-10-10 06:35:03 +02:00
|
|
|
io.ptw.req.valid := state === s_request
|
2016-10-05 07:28:56 +02:00
|
|
|
io.ptw.req.bits <> io.ptw.status
|
2015-03-14 10:49:07 +01:00
|
|
|
io.ptw.req.bits.addr := r_refill_tag
|
2012-10-10 06:35:03 +02:00
|
|
|
|
2016-03-25 22:17:25 +01:00
|
|
|
if (usingVM) {
|
2017-03-14 21:54:49 +01:00
|
|
|
val sfence = io.req.valid && io.req.bits.sfence.valid
|
2016-03-25 22:17:25 +01:00
|
|
|
when (io.req.fire() && tlb_miss) {
|
|
|
|
state := s_request
|
|
|
|
r_refill_tag := lookup_tag
|
|
|
|
r_refill_waddr := repl_waddr
|
|
|
|
r_req := io.req.bits
|
2012-10-10 06:35:03 +02:00
|
|
|
}
|
2016-03-25 22:17:25 +01:00
|
|
|
when (state === s_request) {
|
2017-03-14 21:54:49 +01:00
|
|
|
when (sfence) { state := s_ready }
|
|
|
|
when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) }
|
2016-03-25 22:17:25 +01:00
|
|
|
}
|
2017-03-14 21:54:49 +01:00
|
|
|
when (state === s_wait && sfence) {
|
2016-03-25 22:17:25 +01:00
|
|
|
state := s_wait_invalidate
|
|
|
|
}
|
|
|
|
when (io.ptw.resp.valid) {
|
|
|
|
state := s_ready
|
2012-10-10 06:35:03 +02:00
|
|
|
}
|
2016-07-02 23:26:05 +02:00
|
|
|
|
2017-03-15 20:50:05 +01:00
|
|
|
when (sfence) {
|
2017-07-06 08:53:52 +02:00
|
|
|
assert((io.req.bits.sfence.bits.addr >> pgIdxBits) === vpn(vpnBits-1,0))
|
2017-03-15 20:50:05 +01:00
|
|
|
valid := Mux(io.req.bits.sfence.bits.rs1, valid & ~hits(totalEntries-1, 0),
|
2017-03-27 03:18:35 +02:00
|
|
|
Mux(io.req.bits.sfence.bits.rs2, valid & entries.map(_.g).asUInt, 0))
|
2017-03-14 21:54:49 +01:00
|
|
|
}
|
2017-03-15 20:50:05 +01:00
|
|
|
when (multipleHits) {
|
2016-07-02 23:26:05 +02:00
|
|
|
valid := 0
|
|
|
|
}
|
2012-10-10 06:35:03 +02:00
|
|
|
}
|
|
|
|
}
|