2015-10-06 05:33:55 +02:00
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// See LICENSE for license details.
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package junctions
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import Chisel._
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2015-10-22 03:15:46 +02:00
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import cde.{Parameters, Field}
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2015-10-06 05:33:55 +02:00
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import scala.collection.mutable.HashMap
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2015-10-07 03:14:51 +02:00
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case object PAddrBits extends Field[Int]
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case object VAddrBits extends Field[Int]
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case object PgIdxBits extends Field[Int]
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case object PgLevels extends Field[Int]
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case object PgLevelBits extends Field[Int]
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case object ASIdBits extends Field[Int]
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case object PPNBits extends Field[Int]
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case object VPNBits extends Field[Int]
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case object GlobalAddrMap extends Field[AddrMap]
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trait HasAddrMapParameters {
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implicit val p: Parameters
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val paddrBits = p(PAddrBits)
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val vaddrBits = p(VAddrBits)
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val pgIdxBits = p(PgIdxBits)
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val ppnBits = p(PPNBits)
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val vpnBits = p(VPNBits)
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val pgLevels = p(PgLevels)
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val pgLevelBits = p(PgLevelBits)
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val asIdBits = p(ASIdBits)
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2016-06-03 22:46:53 +02:00
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val addrMap = p(GlobalAddrMap)
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2015-10-07 03:14:51 +02:00
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}
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2016-04-29 01:08:32 +02:00
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case class MemAttr(prot: Int, cacheable: Boolean = false)
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2016-06-03 22:46:53 +02:00
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sealed abstract class MemRegion {
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def start: BigInt
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2016-04-27 23:51:52 +02:00
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def size: BigInt
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def numSlaves: Int
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2016-06-03 22:46:53 +02:00
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def attr: MemAttr
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def containsAddress(x: UInt) = UInt(start) <= x && x < UInt(start + size)
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2016-04-27 23:51:52 +02:00
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}
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2015-10-06 05:33:55 +02:00
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2016-06-03 22:46:53 +02:00
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case class MemSize(size: BigInt, attr: MemAttr) extends MemRegion {
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def start = 0
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2016-04-27 23:51:52 +02:00
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def numSlaves = 1
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}
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2016-06-03 22:46:53 +02:00
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case class MemRange(start: BigInt, size: BigInt, attr: MemAttr) extends MemRegion {
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def numSlaves = 1
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2016-04-27 23:51:52 +02:00
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}
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2015-10-06 05:33:55 +02:00
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2016-04-29 01:08:32 +02:00
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object AddrMapProt {
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2015-12-05 09:26:16 +01:00
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val R = 0x1
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2015-10-06 05:33:55 +02:00
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val W = 0x2
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2015-12-05 09:26:16 +01:00
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val X = 0x4
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2015-10-06 05:33:55 +02:00
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val RW = R | W
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val RX = R | X
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val RWX = R | W | X
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2016-04-29 01:08:32 +02:00
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val SZ = 3
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2015-10-06 05:33:55 +02:00
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}
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class AddrMapProt extends Bundle {
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val x = Bool()
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2015-12-05 09:26:16 +01:00
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val w = Bool()
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val r = Bool()
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2015-10-06 05:33:55 +02:00
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}
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2016-04-27 23:52:05 +02:00
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case class AddrMapEntry(name: String, region: MemRegion)
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2015-10-06 05:33:55 +02:00
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object AddrMap {
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def apply(elems: AddrMapEntry*): AddrMap = new AddrMap(elems)
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}
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2016-06-03 22:46:53 +02:00
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class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) extends MemRegion {
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def isEmpty = entries.isEmpty
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def length = entries.size
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def numSlaves = entries.map(_.region.numSlaves).foldLeft(0)(_ + _)
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2015-10-06 05:33:55 +02:00
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2016-06-03 22:46:53 +02:00
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private val slavePorts = HashMap[String, Int]()
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private val mapping = HashMap[String, MemRegion]()
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2015-10-06 05:33:55 +02:00
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2016-08-10 06:20:54 +02:00
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val (size: BigInt, entries: Seq[AddrMapEntry], attr: MemAttr) = {
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2016-06-03 22:46:53 +02:00
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var ind = 0
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var base = start
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var rebasedEntries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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2016-08-10 06:20:54 +02:00
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var prot = 0
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var cacheable = true
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2016-06-03 22:46:53 +02:00
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for (AddrMapEntry(name, r) <- entriesIn) {
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if (r.start != 0) {
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val align = BigInt(1) << log2Ceil(r.size)
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require(r.start >= base, s"region $name base address 0x${r.start.toString(16)} overlaps previous base 0x${base.toString(16)}")
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base = r.start
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} else {
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base = (base + r.size - 1) / r.size * r.size
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}
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r match {
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case r: AddrMap =>
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val subMap = new AddrMap(r.entries, base)
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rebasedEntries += AddrMapEntry(name, subMap)
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mapping += name -> subMap
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mapping ++= subMap.mapping.map { case (k, v) => s"$name:$k" -> v }
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slavePorts ++= subMap.slavePorts.map { case (k, v) => s"$name:$k" -> (ind + v) }
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case _ =>
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val e = MemRange(base, r.size, r.attr)
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rebasedEntries += AddrMapEntry(name, e)
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mapping += name -> e
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slavePorts += name -> ind
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}
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ind += r.numSlaves
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base += r.size
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2016-08-10 06:20:54 +02:00
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prot |= r.attr.prot
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cacheable &&= r.attr.cacheable
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2015-10-06 05:33:55 +02:00
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}
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2016-08-10 06:20:54 +02:00
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(base - start, rebasedEntries, MemAttr(prot, cacheable))
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2015-10-06 05:33:55 +02:00
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}
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2016-06-03 22:46:53 +02:00
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val flatten: Seq[(String, MemRange)] = {
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val arr = new Array[(String, MemRange)](slavePorts.size)
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for ((name, port) <- slavePorts)
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arr(port) = (name, mapping(name).asInstanceOf[MemRange])
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arr
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2016-04-29 01:08:32 +02:00
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}
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2016-08-10 06:20:54 +02:00
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def toRange: MemRange = MemRange(start, size, attr)
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2016-06-03 22:46:53 +02:00
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def apply(name: String): MemRegion = mapping(name)
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2016-08-04 01:33:30 +02:00
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def contains(name: String): Boolean = mapping.contains(name)
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2016-06-03 22:46:53 +02:00
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def port(name: String): Int = slavePorts(name)
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def subMap(name: String): AddrMap = mapping(name).asInstanceOf[AddrMap]
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def isInRegion(name: String, addr: UInt): Bool = mapping(name).containsAddress(addr)
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2016-04-22 00:33:53 +02:00
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def isCacheable(addr: UInt): Bool = {
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2016-06-03 22:46:53 +02:00
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flatten.filter(_._2.attr.cacheable).map { case (_, region) =>
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region.containsAddress(addr)
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2016-04-29 01:08:32 +02:00
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}.foldLeft(Bool(false))(_ || _)
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2016-04-22 00:33:53 +02:00
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}
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2015-10-06 05:33:55 +02:00
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def isValid(addr: UInt): Bool = {
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2016-06-03 22:46:53 +02:00
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flatten.map { case (_, region) =>
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region.containsAddress(addr)
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2016-04-29 01:08:32 +02:00
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}.foldLeft(Bool(false))(_ || _)
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2015-10-06 05:33:55 +02:00
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}
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def getProt(addr: UInt): AddrMapProt = {
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2016-06-03 22:46:53 +02:00
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val protForRegion = flatten.map { case (_, region) =>
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Mux(region.containsAddress(addr), UInt(region.attr.prot, AddrMapProt.SZ), UInt(0))
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2016-04-29 01:08:32 +02:00
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}
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new AddrMapProt().fromBits(protForRegion.reduce(_|_))
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2015-10-06 05:33:55 +02:00
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}
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}
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