2015-10-06 05:33:55 +02:00
|
|
|
// See LICENSE for license details.
|
|
|
|
|
|
|
|
package junctions
|
|
|
|
|
|
|
|
import Chisel._
|
2015-10-22 03:15:46 +02:00
|
|
|
import cde.{Parameters, Field}
|
2015-10-06 05:33:55 +02:00
|
|
|
import scala.collection.mutable.HashMap
|
|
|
|
|
2015-10-07 03:14:51 +02:00
|
|
|
case object PAddrBits extends Field[Int]
|
|
|
|
case object VAddrBits extends Field[Int]
|
|
|
|
case object PgIdxBits extends Field[Int]
|
|
|
|
case object PgLevels extends Field[Int]
|
|
|
|
case object PgLevelBits extends Field[Int]
|
|
|
|
case object ASIdBits extends Field[Int]
|
|
|
|
case object PPNBits extends Field[Int]
|
|
|
|
case object VPNBits extends Field[Int]
|
|
|
|
|
|
|
|
case object GlobalAddrMap extends Field[AddrMap]
|
|
|
|
|
|
|
|
trait HasAddrMapParameters {
|
|
|
|
implicit val p: Parameters
|
|
|
|
|
|
|
|
val paddrBits = p(PAddrBits)
|
|
|
|
val vaddrBits = p(VAddrBits)
|
|
|
|
val pgIdxBits = p(PgIdxBits)
|
|
|
|
val ppnBits = p(PPNBits)
|
|
|
|
val vpnBits = p(VPNBits)
|
|
|
|
val pgLevels = p(PgLevels)
|
|
|
|
val pgLevelBits = p(PgLevelBits)
|
|
|
|
val asIdBits = p(ASIdBits)
|
|
|
|
|
2016-04-22 00:33:53 +02:00
|
|
|
val addrMap = new AddrHashMap(p(GlobalAddrMap))
|
2015-10-07 03:14:51 +02:00
|
|
|
}
|
|
|
|
|
2015-10-06 05:33:55 +02:00
|
|
|
abstract class MemRegion { def size: BigInt }
|
|
|
|
|
2016-04-22 00:33:53 +02:00
|
|
|
case class MemSize(size: BigInt, prot: Int, cacheable: Boolean = false) extends MemRegion
|
2015-10-06 05:33:55 +02:00
|
|
|
case class MemSubmap(size: BigInt, entries: AddrMap) extends MemRegion
|
|
|
|
|
|
|
|
object AddrMapConsts {
|
2015-12-05 09:26:16 +01:00
|
|
|
val R = 0x1
|
2015-10-06 05:33:55 +02:00
|
|
|
val W = 0x2
|
2015-12-05 09:26:16 +01:00
|
|
|
val X = 0x4
|
2015-10-06 05:33:55 +02:00
|
|
|
val RW = R | W
|
|
|
|
val RX = R | X
|
|
|
|
val RWX = R | W | X
|
|
|
|
}
|
|
|
|
|
|
|
|
class AddrMapProt extends Bundle {
|
|
|
|
val x = Bool()
|
2015-12-05 09:26:16 +01:00
|
|
|
val w = Bool()
|
|
|
|
val r = Bool()
|
2015-10-06 05:33:55 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
case class AddrMapEntry(name: String, start: Option[BigInt], region: MemRegion)
|
|
|
|
|
2016-04-22 00:33:53 +02:00
|
|
|
case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt, prot: Int, cacheable: Boolean)
|
2015-10-06 05:33:55 +02:00
|
|
|
|
|
|
|
class AddrMap(entries: Seq[AddrMapEntry]) extends scala.collection.IndexedSeq[AddrMapEntry] {
|
|
|
|
|
|
|
|
def apply(index: Int): AddrMapEntry = entries(index)
|
|
|
|
|
|
|
|
def length: Int = entries.size
|
|
|
|
|
|
|
|
def countSlaves: Int = {
|
|
|
|
this map { entry: AddrMapEntry => entry.region match {
|
2016-04-22 00:33:53 +02:00
|
|
|
case MemSize(_, _, _) => 1
|
2015-10-06 05:33:55 +02:00
|
|
|
case MemSubmap(_, submap) => submap.countSlaves
|
|
|
|
}} reduceLeft(_ + _)
|
|
|
|
}
|
2016-04-22 00:33:53 +02:00
|
|
|
|
|
|
|
override def tail: AddrMap = new AddrMap(entries.tail)
|
2015-10-06 05:33:55 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
object AddrMap {
|
|
|
|
def apply(elems: AddrMapEntry*): AddrMap = new AddrMap(elems)
|
|
|
|
}
|
|
|
|
|
2016-04-22 00:33:53 +02:00
|
|
|
class AddrHashMap(addrmap: AddrMap, start: BigInt = BigInt(0)) {
|
2015-10-06 05:33:55 +02:00
|
|
|
val mapping = new HashMap[String, AddrHashMapEntry]
|
|
|
|
|
2016-01-15 01:41:32 +01:00
|
|
|
private def genPairs(am: AddrMap, start: BigInt): Seq[(String, AddrHashMapEntry)] = {
|
2015-10-06 05:33:55 +02:00
|
|
|
var ind = 0
|
2016-01-15 01:41:32 +01:00
|
|
|
var base = start
|
2015-10-06 05:33:55 +02:00
|
|
|
var pairs = Seq[(String, AddrHashMapEntry)]()
|
|
|
|
am.foreach { case AddrMapEntry(name, startOpt, region) =>
|
|
|
|
region match {
|
2016-04-22 00:33:53 +02:00
|
|
|
case MemSize(size, prot, cacheable) => {
|
2015-10-06 05:33:55 +02:00
|
|
|
if (!startOpt.isEmpty) base = startOpt.get
|
2016-04-22 00:33:53 +02:00
|
|
|
pairs = (name, AddrHashMapEntry(ind, base, size, prot, cacheable)) +: pairs
|
2015-10-06 05:33:55 +02:00
|
|
|
base += size
|
|
|
|
ind += 1
|
|
|
|
}
|
|
|
|
case MemSubmap(size, submap) => {
|
|
|
|
if (!startOpt.isEmpty) base = startOpt.get
|
2016-01-15 01:41:32 +01:00
|
|
|
val subpairs = genPairs(submap, base).map {
|
2016-04-22 00:33:53 +02:00
|
|
|
case (subname, AddrHashMapEntry(subind, subbase, subsize, prot, cacheable)) =>
|
2015-10-06 05:33:55 +02:00
|
|
|
(name + ":" + subname,
|
2016-04-22 00:33:53 +02:00
|
|
|
AddrHashMapEntry(ind + subind, subbase, subsize, prot, cacheable))
|
2015-10-06 05:33:55 +02:00
|
|
|
}
|
|
|
|
pairs = subpairs ++ pairs
|
|
|
|
ind += subpairs.size
|
|
|
|
base += size
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
pairs
|
|
|
|
}
|
|
|
|
|
2016-01-15 01:41:32 +01:00
|
|
|
for ((name, ind) <- genPairs(addrmap, start)) { mapping(name) = ind }
|
2015-10-06 05:33:55 +02:00
|
|
|
|
|
|
|
def nEntries: Int = mapping.size
|
|
|
|
def apply(name: String): AddrHashMapEntry = mapping(name)
|
|
|
|
def get(name: String): Option[AddrHashMapEntry] = mapping.get(name)
|
2016-04-22 00:33:53 +02:00
|
|
|
def sortedEntries(): Seq[(String, BigInt, BigInt, Int, Boolean)] = {
|
|
|
|
val arr = new Array[(String, BigInt, BigInt, Int, Boolean)](mapping.size)
|
|
|
|
mapping.foreach { case (name, AddrHashMapEntry(port, base, size, prot, cacheable)) =>
|
|
|
|
arr(port) = (name, base, size, prot, cacheable)
|
2015-10-06 05:33:55 +02:00
|
|
|
}
|
|
|
|
arr.toSeq
|
|
|
|
}
|
|
|
|
|
2016-04-22 00:33:53 +02:00
|
|
|
def isInRegion(name: String, addr: UInt): Bool = {
|
|
|
|
val start = mapping(name).start
|
|
|
|
val size = mapping(name).size
|
|
|
|
UInt(start) <= addr && addr < UInt(start + size)
|
|
|
|
}
|
|
|
|
|
|
|
|
def isCacheable(addr: UInt): Bool = {
|
|
|
|
sortedEntries().map { case (_, base, size, _, cacheable) =>
|
|
|
|
UInt(base) <= addr && addr < UInt(base + size) && Bool(cacheable)
|
|
|
|
}.reduce(_ || _)
|
|
|
|
}
|
|
|
|
|
2015-10-06 05:33:55 +02:00
|
|
|
def isValid(addr: UInt): Bool = {
|
2016-01-15 01:41:32 +01:00
|
|
|
addr < UInt(start) || sortedEntries().map {
|
2016-04-22 00:33:53 +02:00
|
|
|
case (_, base, size, _, _) =>
|
2016-01-15 01:41:32 +01:00
|
|
|
addr >= UInt(base) && addr < UInt(base + size)
|
2015-10-06 05:33:55 +02:00
|
|
|
}.reduceLeft(_ || _)
|
|
|
|
}
|
|
|
|
|
|
|
|
def getProt(addr: UInt): AddrMapProt = {
|
2016-01-15 01:41:32 +01:00
|
|
|
val protBits = Mux(addr < UInt(start),
|
|
|
|
Bits(AddrMapConsts.RWX, 3),
|
2016-04-22 00:33:53 +02:00
|
|
|
Mux1H(sortedEntries().map { case (_, base, size, prot, _) =>
|
2016-01-15 01:41:32 +01:00
|
|
|
(addr >= UInt(base) && addr < UInt(base + size), Bits(prot, 3))
|
|
|
|
}))
|
|
|
|
new AddrMapProt().fromBits(protBits)
|
2015-10-06 05:33:55 +02:00
|
|
|
}
|
|
|
|
}
|