Add terminal/dvi io (unsing the same clock for now)

src/main/scala/ip/xilinx/Xilinx.scala

@@ -99,6 +99,7 @@ class ml507_sys_clock extends BlackBox {
   val io = new Bundle {
     val CLKIN_IN  = Bool(INPUT)
     val CLKFX_OUT = Clock(OUTPUT)
+    val LOCKED_OUT = Bool(OUTPUT)
   }
 }
 

src/main/scala/shell/xilinx/ML507Shell.scala

@@ -13,6 +13,7 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.chiplink._
+import sifive.blocks.devices.terminal._
 
 import sifive.fpgashells.ip.xilinx.{IBUFDS, PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_sys_clock , vc707reset}
 
@@ -30,47 +31,6 @@ trait HasDebugJTAG { this: ML507Shell =>
   val jtag_TDO             = IO(Output(Bool()))
 
   def connectDebugJTAG(dut: HasPeripheryDebugModuleImp, fmcxm105: Boolean = true): SystemJTAGIO = {
-
-    ElaborationArtefacts.add(
-    """debugjtag.vivado.tcl""",
-    """set vc707debugjtag_vivado_tcl_dir [file dirname [file normalize [info script]]]
-       add_files -fileset [current_fileset -constrset] [glob -directory $vc707debugjtag_vivado_tcl_dir {*.vc707debugjtag.xdc}]"""
-    )
-
-    if(fmcxm105) {
-      //VC707 constraints for Xilinx FMC XM105 Debug Card
-      ElaborationArtefacts.add(
-        """vc707debugjtag.xdc""",
-        """set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
-           set_property -dict { PACKAGE_PIN R32  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TCK}]
-           set_property -dict { PACKAGE_PIN W36  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TMS}]
-           set_property -dict { PACKAGE_PIN W37  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TDI}]
-           set_property -dict { PACKAGE_PIN V40  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TDO}] """
-      )
-    } else {
-      //VC707 constraints for Olimex connect to LCD panel header
-     ElaborationArtefacts.add(
-        """vc707debugjtag.xdc""",
-        """
-           #Olimex Pin  Olimex Function LCD Pin LCD Function FPGA Pin
-           #1           VREF            14      5V
-           #3           TTRST_N         1       LCD_DB7       AN40
-           #5           TTDI            2       LCD_DB6       AR39
-           #7           TTMS            3       LCD_DB5       AR38
-           #9           TTCK            4       LCD_DB4       AT42
-           #11          TRTCK           NC      NC            NC
-           #13          TTDO            9       LCD_E         AT40
-           #15          TSRST_N         10      LCD_RW        AR42
-           #2           VREF            14      5V
-           #18          GND             13      GND
-           set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
-           set_property -dict { PACKAGE_PIN AT42  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TCK}]
-           set_property -dict { PACKAGE_PIN AR38  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TMS}]
-           set_property -dict { PACKAGE_PIN AR39  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TDI}]
-           set_property -dict { PACKAGE_PIN AT40  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TDO}] """
-      )
-    }
-
     val djtag     = dut.debug.systemjtag.get
 
     djtag.jtag.TCK := jtag_TCK
@@ -98,7 +58,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
 
   // active high reset
   val reset                = IO(Input(Bool()))
-  val reset_led            = IO(Output(Bool()))
 
   // LED
   val led                  = IO(Vec(8, Output(Bool())))
@@ -113,21 +72,26 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
   val sdio_dat             = IO(Analog(4.W))
 
   //Buttons
-  val btn_0                = IO(Analog(1.W))
+  val btn_0                = IO(Input(Bool()))
-  val btn_1                = IO(Analog(1.W))
+  val btn_1                = IO(Input(Bool()))
-  val btn_2                = IO(Analog(1.W))
+  val btn_2                = IO(Input(Bool()))
-  val btn_3                = IO(Analog(1.W))
+  val btn_3                = IO(Input(Bool()))
 
   //Sliding switches
-  val sw_0                 = IO(Analog(1.W))
+  val sw_0                 = IO(Input(Bool()))
-  val sw_1                 = IO(Analog(1.W))
+  val sw_1                 = IO(Input(Bool()))
-  val sw_2                 = IO(Analog(1.W))
+  val sw_2                 = IO(Input(Bool()))
-  val sw_3                 = IO(Analog(1.W))
+  val sw_3                 = IO(Input(Bool()))
-  val sw_4                 = IO(Analog(1.W))
+  val sw_4                 = IO(Input(Bool()))
-  val sw_5                 = IO(Analog(1.W))
+  val sw_5                 = IO(Input(Bool()))
-  val sw_6                 = IO(Analog(1.W))
+  val sw_6                 = IO(Input(Bool()))
-  val sw_7                 = IO(Analog(1.W))
+  val sw_7                 = IO(Input(Bool()))
 
+  // Feedback
+  val clock_led            = IO(Output(Clock()))
+  val reset_led            = IO(Output(Bool()))
+
+  val dvi                  = IO(new TerminalDVIIO)
 
   //-----------------------------------------------------------------------
   // Wire declrations
@@ -138,7 +102,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
 
   val dut_clock       = Wire(Clock())
   val dut_reset       = Wire(Bool())
-  val dut_resetn      = Wire(Bool())
 
   val dut_ndreset     = Wire(Bool())
 
@@ -149,20 +112,7 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
 
   val do_reset        = Wire(Bool())
 
-  val mig_mmcm_locked = Wire(Bool())
+  val clk_locked      = Wire(Bool())
-  val mig_sys_reset   = Wire(Bool())
-
-  val mig_clock       = Wire(Clock())
-  val mig_reset       = Wire(Bool())
-  val mig_resetn      = Wire(Bool())
-
-  val pcie_dat_reset  = Wire(Bool())
-  val pcie_dat_resetn = Wire(Bool())
-  val pcie_cfg_reset  = Wire(Bool())
-  val pcie_cfg_resetn = Wire(Bool())
-  val pcie_dat_clock  = Wire(Clock())
-  val pcie_cfg_clock  = Wire(Clock())
-  val mmcm_lock_pcie  = Wire(Bool())
 
 
   //-----------------------------------------------------------------------
@@ -175,17 +125,15 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
   // Allow the debug module to reset everything. Resets the MIG
   sys_reset := reset | dut_ndreset
 
-  // Status LED for reset
-  reset_led := reset
-
   //-----------------------------------------------------------------------
   // Clock Generator
   //-----------------------------------------------------------------------
 
-  //50MHz (37.5MHz)
+  // 48 MHz (TMP, normally 50 MHz)
   val ml507_sys_clock = Module(new ml507_sys_clock)
   ml507_sys_clock.io.CLKIN_IN := sys_clock.asUInt
   val clk50 = ml507_sys_clock.io.CLKFX_OUT
+  clk_locked := ml507_sys_clock.io.LOCKED_OUT
 
   // DUT clock
   dut_clock := clk50
@@ -194,34 +142,31 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
   // System reset
   //-----------------------------------------------------------------------
 
-  do_reset             := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset
+  do_reset             := !clk_locked || sys_reset
-  mig_resetn           := !mig_reset
-  dut_resetn           := !dut_reset
-  pcie_dat_resetn      := !pcie_dat_reset
-  pcie_cfg_resetn      := !pcie_cfg_reset
 
   // TODO: adapt for ml507?
   val safe_reset = Module(new vc707reset)
 
   safe_reset.io.areset := do_reset
-  safe_reset.io.clock1 := mig_clock
+  safe_reset.io.clock1 := dut_clock
-  mig_reset            := safe_reset.io.reset1
+  safe_reset.io.clock2 := dut_clock
-  safe_reset.io.clock2 := pcie_dat_clock
+  safe_reset.io.clock3 := dut_clock
-  pcie_dat_reset       := safe_reset.io.reset2
-  safe_reset.io.clock3 := pcie_cfg_clock
-  pcie_cfg_reset       := safe_reset.io.reset3
   safe_reset.io.clock4 := dut_clock
   dut_reset            := safe_reset.io.reset4
 
-  //overrided in connectMIG and connect PCIe
+  // Setup feedback
-  //provide defaults to allow above reset sequencing logic to work without both
+  clock_led := dut_clock
-  mig_clock            := dut_clock
+  reset_led := dut_reset
-  pcie_dat_clock       := dut_clock
-  pcie_cfg_clock       := dut_clock
-  mig_mmcm_locked      := UInt("b1")
-  mmcm_lock_pcie       := UInt("b1")
 
+  //-----------------------------------------------------------------------
+  // Terminal
+  //-----------------------------------------------------------------------
 
+  def connectTerminal(dut: HasPeripheryTerminalModuleImp): Unit = {
+    dvi <> dut.dvi
+    dut.terminal.clk := dut_clock
+    dut.terminal.reset := dut_reset
+  }
 
   //-----------------------------------------------------------------------
   // UART