Klemens Schölhorn
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b49f5cfa78
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Reduce crossing and queue depths to save space and ease timing
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2018-05-14 20:07:01 +02:00 |
Klemens Schölhorn
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700e6b640d
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Document address extraction for the mig
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2018-05-13 19:52:38 +02:00 |
Klemens Schölhorn
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12cb1c2fa5
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Implement XilinxML507MIGToTL TL to MIG converter
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2018-05-10 21:40:52 +02:00 |
Klemens Schölhorn
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7e53be49f9
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Fix memory controller signal name
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2018-05-10 02:27:31 +02:00 |
Klemens Schölhorn
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589e9960c0
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Move XilinxML507MIGToTL and MIG into a separate clock domain
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2018-05-10 00:30:23 +02:00 |
Klemens Schölhorn
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2707fa59a4
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Add XilinxML507MIG periphery and connect top level signals
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2018-05-10 00:29:22 +02:00 |
Klemens Schölhorn
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3797385a8c
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Import ml507 mig TL implementation stub
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2018-05-09 23:17:08 +02:00 |