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20 Commits

Author SHA1 Message Date
Wesley W. Terpstra 1dda525578 prologue: support the absence of an xdc/tcl constraint file 2018-02-25 15:21:03 -08:00
Wesley W. Terpstra 4386187016 vc707: add clock groups dynamically iff they exist 2018-02-25 14:33:32 -08:00
Wesley W. Terpstra b7afc83a34 xilinx prologue: support tcl for constraints 2018-02-25 14:32:39 -08:00
Wesley W. Terpstra 8519ba8d4e vc707: setup 100MHz PLL 2018-02-08 07:21:45 -08:00
Wesley W. Terpstra 506d2da883 vc707: update constraints to match correct mmcm 2018-02-08 07:21:45 -08:00
Henry Styles 045b290fbd VC707 JTAG support throught XM105 FMC or reuse of LCD header 2018-02-08 07:21:44 -08:00
Henry Styles e1bfb75188 VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock 2017-11-01 14:23:07 -07:00
Henry Styles dc6bb40d1b VC707 : update contraints file to match PCIe and MIG signal names now claimed directly from the IP 2017-10-23 17:27:36 -07:00
Richard Xia 9593e5eee6 Restructure Tcl script entrypoint. 
vivado.tcl is now the entrypoint for the Vivado Tcl scripts and will
automatically source all the other required scripts.

A command line argument parser was written and replaces the previous system of
using environment variables to pass values into the scripts. The VSRCSVIVADOTCL
environment variable has been replaced with a -F command line option, and the
file format has changed from a Tcl script to a simple newline-delimited list of
files.
 2017-10-04 14:15:39 -07:00
Henry Styles 97e628639a Use a file instead of environment variable to pass VSRCS into Vivado 2017-09-19 14:12:23 -07:00
Henry Styles 2bed0c30dc correct invoke of board specific ip.tcl 2017-09-08 23:20:55 -07:00
Henry Styles 9f75e6eb59 Support both 4G and 1GB DIMM configuration for VC707 
Generate IP TCL and MIG projects from the Chisel blackboxes
 2017-09-08 15:52:53 -07:00
Megan Wachs 31650a2d23 Merge remote-tracking branch 'origin/master' into synchronizers 2017-09-07 10:46:03 -07:00
Henry Styles b7ee0ab0f0 fix PCIe vc707 design contraints : PCIe pins and UART RX sync register 2017-09-07 10:41:12 -07:00
Megan Wachs cab572fab2 synchronizers: decided that ShiftRegInit should be reversed as the others. 2017-09-07 09:54:35 -07:00
Megan Wachs fd70d118d3 synchronizers: Update constraints to match new hierarchy for synchronizers 2017-09-07 07:50:22 -07:00
Shreesha Srinath 38afe2957f Fixing typos in the tcl script 2017-08-18 11:34:35 -07:00
Shreesha Srinath ae767458af Pass debug hooks through project-specific makefiles 2017-08-18 11:27:02 -07:00
Shreesha Srinath c58e79f155 vc707: Updates to the constraints and shell 2017-08-17 18:51:01 -07:00
Shreesha Srinath ab8cf0775f Initial commit for fpga-shells 2017-08-16 11:23:45 -07:00