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Commit Graph

20 Commits

Author SHA1 Message Date
Alex Solomatnikov
a915e84a9e Merge remote-tracking branch 'origin/master' into i2c 2017-02-09 18:45:35 -08:00
Alex Solomatnikov
095cb158dd Flipped polarity of output enables to match Guava pins logic 2017-02-09 11:37:40 -08:00
Alex Solomatnikov
72e4b60d81 Made regs 32-bit word aligned to match the rest of the system 2017-02-09 11:36:19 -08:00
Alex Solomatnikov
9ca71c0cf2 Added note: WISHBONE interface replaced by Tilelink2 2017-02-07 16:14:28 -08:00
Alex Solomatnikov
c311b6ec63 Added license 2017-02-07 15:58:04 -08:00
Alex Solomatnikov
5a0d084b38 Renamed i2cDevices to i2c 2017-02-06 10:39:47 -08:00
Wesley W. Terpstra
88e4c8ee20 xilinx mig: track changes in rocket-chip 2017-02-03 18:17:58 -08:00
Alex Solomatnikov
d474b5ceb2 Addressing comments: bool style, comments, removed suggestName 2017-02-03 18:10:03 -08:00
Alex Solomatnikov
3781d1fb1a Bug fixes: passing OC WB test 2017-02-03 16:41:59 -08:00
Wesley W. Terpstra
c010a1557a sifive-blocks: trust diplomacy to get names right 2017-02-01 13:53:54 -08:00
Alex Solomatnikov
2cc1012fa2 Completed Chisel RTL (not tested yet) 2017-01-31 17:20:53 -08:00
Wesley W. Terpstra
535be3e976 spi: work around ucb-bar/chisel3#472 2017-01-31 14:03:14 -08:00
Wesley W. Terpstra
5b6760394d xilinx ip: adjust to new diplomacy API 2017-01-30 11:33:30 -08:00
Alex Solomatnikov
9d2a173b15 Initial (compilable) version of I2C (no actual logic yet) 2017-01-24 14:58:01 -08:00
Wesley W. Terpstra
d61d86e084 xilinx pcie: put buffers before the outputs to the controller 2017-01-20 22:38:27 -08:00
Wesley W. Terpstra
c68e44ec55 mig: track change to Blind port API in rocket 2017-01-19 19:53:03 -08:00
Wesley W. Terpstra
45c491cd69 LazyModule: provide Parameters
This tracks PR #478 in rocketchip.
2016-12-07 13:21:20 -08:00
Wesley W. Terpstra
1443834186 xilinx pcie: bytes, not bits
This bug amazingly compiled correctly and ran correctly!

It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.

The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
2016-12-06 16:13:12 -08:00
Wesley W. Terpstra
ca7555bd4d RegMapFIFO: amoor.w can do thread-safe TX 2016-12-02 17:48:17 -08:00
SiFive
7916ef5249 Initial commit. 2016-11-29 04:08:44 -08:00