| .. |
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arbiter.scala
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Use HeaderlessTileLinkIO
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2015-04-13 15:58:10 -07:00 |
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btb.scala
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Specify some uninferrable widths
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2015-07-31 14:23:52 -07:00 |
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consts.scala
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Chisel3 compatibility: use BitPat for don't-cares
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2015-07-28 02:48:49 -07:00 |
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csr.scala
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Purge UInt := SInt assignments
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2015-07-31 15:42:10 -07:00 |
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decode.scala
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Use Seq, not Iterable, when traversal order matters
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2015-07-29 00:24:58 -07:00 |
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dpath_alu.scala
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Chisel3 compatibility: use BitPat for don't-cares
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2015-07-28 02:48:49 -07:00 |
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fpu.scala
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Purge UInt := SInt assignments
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2015-07-31 15:42:10 -07:00 |
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icache.scala
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Chisel3: bulk connect is not commutative
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2015-08-01 21:11:25 -07:00 |
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idecode.scala
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Chisel3 has different Vec semantics
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2015-08-03 19:08:00 -07:00 |
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instructions.scala
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Chisel3 compatibility: use BitPat for don't-cares
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2015-07-28 02:48:49 -07:00 |
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multiplier.scala
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Purge UInt := SInt assignments
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2015-07-31 15:42:10 -07:00 |
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nbdcache.scala
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Chisel3: Flip order of := and <>
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2015-08-03 18:53:09 -07:00 |
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package.scala
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Update to privileged architecture 1.7
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2015-05-19 02:32:21 -07:00 |
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ptw.scala
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Chisel3 compatibility potpourri
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2015-07-30 23:53:02 -07:00 |
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rocc.scala
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Chisel3 compatibility changes
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2015-07-27 12:42:20 -07:00 |
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rocket.scala
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Bits -> UInt
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2015-08-02 21:03:42 -07:00 |
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tile.scala
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Chisel3: bulk connect is not commutative
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2015-08-01 21:11:25 -07:00 |
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tlb.scala
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Purge UInt := SInt assignments
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2015-07-31 15:42:10 -07:00 |
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util.scala
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Use Seq, not Iterable, when traversal order matters
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2015-07-29 00:24:58 -07:00 |
