Rimas Avizienis c580180b66 tweaks to cache/SRAM interface for TSMC65 SRAMs

2011-12-02 02:01:08 -08:00

..

arbiter.scala

more itlb integration & cleanup

2011-11-09 23:18:14 -08:00

consts.scala

bugfixes due to new hcl jar file

2011-11-30 21:54:55 -08:00

cpu.scala

fixed console i/o

2011-11-30 22:51:59 -08:00

ctrl_util.scala

initial commit of rocket chisel project, riscv assembly tests and benchmarks

2011-10-25 23:02:47 -07:00

ctrl.scala

changed branch addr generation to get it off critical path

2011-12-02 01:56:17 -08:00

dcache.scala

tweaks to cache/SRAM interface for TSMC65 SRAMs

2011-12-02 02:01:08 -08:00

divider.scala

initial commit of rocket chisel project, riscv assembly tests and benchmarks

2011-10-25 23:02:47 -07:00

dpath_alu.scala

more itlb integration & cleanup

2011-11-09 23:18:14 -08:00

dpath_util.scala

fixed console i/o

2011-11-30 22:51:59 -08:00

dpath.scala

changed branch addr generation to get it off critical path

2011-12-02 01:56:17 -08:00

dtlb.scala

fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions

2011-11-17 11:17:37 -08:00

icache_prefetch.scala

Merge branch 'master' of github.com:ucb-bar/riscv-rocket

2011-11-30 21:55:13 -08:00

icache.scala

tweaks to cache/SRAM interface for TSMC65 SRAMs

2011-12-02 02:01:08 -08:00

instructions.scala

cleanup

2011-11-15 18:06:41 -08:00

itlb.scala

more cache fixes, more test harness debug output

2011-11-13 23:32:18 -08:00

multiplier.scala

initial commit of rocket chisel project, riscv assembly tests and benchmarks

2011-10-25 23:02:47 -07:00

ptw.scala

more itlb/dtlb/ptw fixes

2011-11-12 15:00:45 -08:00

queues.scala

queue data type is now templated

2011-11-30 18:08:26 -08:00

top.scala

integrating ITLB & PTW

2011-11-09 14:52:17 -08:00

util.scala

cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB

2011-11-10 11:26:13 -08:00