230 lines
6.5 KiB
Scala
230 lines
6.5 KiB
Scala
package queues
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{
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import Chisel._
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import Node._;
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import scala.math._;
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class ioQueueCtrl(addr_sz: Int) extends Bundle()
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{
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val q_reset = Bool('input);
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val enq_val = Bool('input);
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val enq_rdy = Bool('output);
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val deq_val = Bool('output);
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val deq_rdy = Bool('input);
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val wen = Bool('output);
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val waddr = UFix(addr_sz, 'output);
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val raddr = UFix(addr_sz, 'output);
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}
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class queueCtrl(entries: Int) extends Component
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{
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val addr_sz = ceil(log(entries)/log(2)).toInt
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override val io = new ioQueueCtrl(addr_sz);
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// Enqueue and dequeue pointers
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val enq_ptr = Reg(width = addr_sz, resetVal = UFix(0, addr_sz));
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val deq_ptr = Reg(width = addr_sz, resetVal = UFix(0, addr_sz));
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val full = Reg(width = 1, resetVal = Bool(false));
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when (io.q_reset) {
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enq_ptr <== UFix(0, addr_sz);
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deq_ptr <== UFix(0, addr_sz);
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full <== Bool(false);
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}
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io.waddr := enq_ptr;
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io.raddr := deq_ptr;
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// We enq/deq only when they are both ready and valid
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val do_enq = io.enq_rdy && io.enq_val;
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val do_deq = io.deq_rdy && io.deq_val;
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// Determine if we have pipeline or flowthrough behaviour and
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// set the write enable accordingly.
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val empty = ~full && (enq_ptr === deq_ptr);
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io.wen := do_enq;
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// Ready signals are calculated from full register. If pipeline
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// behavior is enabled, then the enq_rdy signal is also calculated
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// combinationally from the deq_rdy signal. If flowthrough behavior
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// is enabled then the deq_val signal is also calculated combinationally
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// from the enq_val signal.
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io.enq_rdy := ~full;
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io.deq_val := ~empty;
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// Control logic for the enq/deq pointers and full register
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val deq_ptr_inc = deq_ptr + UFix(1, 1);
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val enq_ptr_inc = enq_ptr + UFix(1, 1);
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val deq_ptr_next =
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Mux(do_deq, deq_ptr_inc,
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deq_ptr);
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val enq_ptr_next =
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Mux(do_enq, enq_ptr_inc,
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enq_ptr);
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val full_next =
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Mux(do_enq && ~do_deq && ( enq_ptr_inc === deq_ptr ), Bool(true),
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Mux(do_deq && full, Bool(false),
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full));
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enq_ptr <== enq_ptr_next;
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deq_ptr <== deq_ptr_next;
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full <== full_next;
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}
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class ioQueueSimplePF[T <: Data]()(data: => T) extends Bundle()
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{
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val q_reset = Bool('input);
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val enq_val = Bool('input);
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val enq_rdy = Bool('output);
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val deq_val = Bool('output);
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val deq_rdy = Bool('input);
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val enq_bits = data.asInput;
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val deq_bits = data.asOutput;
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}
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class queueSimplePF[T <: Data](entries: Int)(data: => T) extends Component
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{
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override val io = new ioQueueSimplePF()(data);
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val ctrl = new queueCtrl(entries);
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ctrl.io.q_reset ^^ io.q_reset;
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ctrl.io.deq_val ^^ io.deq_val;
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ctrl.io.enq_rdy ^^ io.enq_rdy;
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ctrl.io.enq_val ^^ io.enq_val;
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ctrl.io.deq_rdy ^^ io.deq_rdy;
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val ram = Mem(entries, ctrl.io.wen, ctrl.io.waddr, io.enq_bits);
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ram.read(ctrl.io.raddr) ^^ io.deq_bits;
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}
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// TODO: SHOULD USE INHERITANCE BUT BREAKS INTROSPECTION CODE
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// class IOqueueCtrlFlow extends IOqueueCtrl
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class ioQueueCtrlFlow(addr_sz: Int) extends Bundle() /* IOqueueCtrl */
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{
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val enq_val = Bool('input);
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val enq_rdy = Bool('output);
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val deq_val = Bool('output);
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val deq_rdy = Bool('input);
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val wen = Bool('output);
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val waddr = UFix(addr_sz, 'output);
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val raddr = UFix(addr_sz, 'output);
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val flowthru = Bool('output);
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}
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class queueCtrlFlow(entries: Int) extends Component
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{
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val addr_sz = ceil(log(entries)/log(2)).toInt
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override val io = new ioQueueCtrlFlow(addr_sz);
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// Enqueue and dequeue pointers
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val enq_ptr = Reg(width = addr_sz, resetVal = UFix(0, addr_sz));
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val deq_ptr = Reg(width = addr_sz, resetVal = UFix(0, addr_sz));
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val full = Reg(width = 1, resetVal = Bool(false));
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io.waddr := enq_ptr;
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io.raddr := deq_ptr;
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// We enq/deq only when they are both ready and valid
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val do_enq = io.enq_rdy && io.enq_val;
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val do_deq = io.deq_rdy && io.deq_val;
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// Determine if we have pipeline or flowthrough behaviour and
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// set the write enable accordingly.
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val empty = ~full && (enq_ptr === deq_ptr);
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val do_flowthru = empty && do_enq && do_deq;
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io.flowthru := do_flowthru;
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io.wen := do_enq && ~do_flowthru;
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// Ready signals are calculated from full register. If pipeline
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// behavior is enabled, then the enq_rdy signal is also calculated
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// combinationally from the deq_rdy signal. If flowthrough behavior
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// is enabled then the deq_val signal is also calculated combinationally
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// from the enq_val signal.
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io.enq_rdy := ~full;
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io.deq_val := ~empty || ( empty && io.enq_val );
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// Control logic for the enq/deq pointers and full register
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val deq_ptr_inc = deq_ptr + UFix(1, 1);
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val enq_ptr_inc = enq_ptr + UFix(1, 1);
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val deq_ptr_next =
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Mux(do_deq && ~do_flowthru, deq_ptr_inc,
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deq_ptr);
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val enq_ptr_next =
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Mux(do_enq && ~do_flowthru, enq_ptr_inc,
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enq_ptr);
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val full_next =
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Mux(do_enq && ~do_deq && ( enq_ptr_inc === deq_ptr ), Bool(true),
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Mux(do_deq && full, Bool(false),
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full));
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enq_ptr <== enq_ptr_next;
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deq_ptr <== deq_ptr_next;
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full <== full_next;
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}
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class ioQueueDpathFlow[T <: Data](addr_sz: Int)(data: => T) extends Bundle()
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{
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val wen = Bool('input);
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val flowthru = Bool('input);
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val deq_bits = data.asOutput;
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val enq_bits = data.asInput;
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val waddr = UFix(addr_sz, 'input);
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val raddr = UFix(addr_sz, 'input);
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}
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class queueDpathFlow[T <: Data](entries: Int)(data: => T) extends Component
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{
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val addr_sz = ceil(log(entries)/log(2)).toInt
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override val io = new ioQueueDpathFlow(addr_sz)(data);
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val ram = Mem(entries, io.wen, io.waddr, io.enq_bits);
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val rout = ram(io.raddr);
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Mux(io.flowthru, io.enq_bits, rout) ^^ io.deq_bits;
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}
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class ioQueueFlowPF[T <: Data](data: => T) extends Bundle()
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{
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val enq_val = Bool('input);
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val enq_rdy = Bool('output);
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val enq_bits = data.asInput;
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val deq_val = Bool('output);
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val deq_rdy = Bool('input);
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val deq_bits = data.asOutput;
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}
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class queueFlowPF[T <: Data](entries: Int)(data: => T) extends Component
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{
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override val io = new ioQueueFlowPF(data);
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val ctrl = new queueCtrlFlow(entries);
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val dpath = new queueDpathFlow(entries)(data);
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ctrl.io.deq_rdy ^^ io.deq_rdy;
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ctrl.io.wen <> dpath.io.wen;
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ctrl.io.raddr <> dpath.io.raddr;
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ctrl.io.waddr <> dpath.io.waddr;
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ctrl.io.flowthru <> dpath.io.flowthru;
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ctrl.io.enq_val ^^ io.enq_val;
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dpath.io.enq_bits ^^ io.enq_bits;
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ctrl.io.deq_val ^^ io.deq_val;
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ctrl.io.enq_rdy ^^ io.enq_rdy;
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dpath.io.deq_bits ^^ io.deq_bits;
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}
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}
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