Howard Mao 7b7e954133 make sure DummyPTW does not invalidate the TLB		2016-03-22 19:59:58 -07:00
..
cachetest.scala	add DMA test	2015-12-16 21:26:22 -08:00
dmatest.scala	use MMIO for DMA requests instead of separate channel	2016-01-27 15:33:02 -08:00
generator.scala	Work around Chisel3's lack of 0-width wires	2016-03-14 22:50:37 -07:00
nastitest.scala	add test for NASTI to TL converter	2016-02-10 11:07:37 -08:00
regression.scala	get rid of sequential same id get regression in broadcast regression suite	2016-02-19 23:14:34 -08:00
tile.scala	make sure DummyPTW does not invalidate the TLB	2016-03-22 19:59:58 -07:00
tracegen.scala	Updates to the trace-generator: (1) Don't terminate via HTIF exit, which can cause other, unfinished, cores to be cut short. Instead emit FINISHED messsages allowing an external process to send a SIGTERM to the emulator once all cores have finished. (2) Add some support for greater address variation without having to recompile, disabled by default. (3) Generate atomic, LR/SC, and fence operations by default in addition to plain loads and stores. These changes require newer versions of files in the rocket-chip/scripts directory. I will submit a pull request for those too.	2016-03-18 12:11:11 +00:00
unittest.scala	add NastiIOHostIO converter test	2016-02-19 11:21:53 -08:00
util.scala	Avoid conflicting assigments to registers in timers. Give priority to start over stop.	2016-03-16 12:54:19 -07:00