126 lines
3.8 KiB
Scala
126 lines
3.8 KiB
Scala
package groundtest
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import Chisel._
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import uncore._
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import junctions._
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import cde.Parameters
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abstract class NastiTest(implicit val p: Parameters) extends Module
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with HasNastiParameters with HasMIFParameters {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val mem = new NastiIO
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}
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}
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class NastiBlockTest(implicit p: Parameters) extends NastiTest()(p) {
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val s_start :: s_write :: s_read :: s_wait :: s_finish :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_start)
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val addr_sent = Reg(init = Bool(false))
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val data_sent = Reg(init = UInt(0, mifDataBeats))
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val write_acked = Reg(init = Bool(false))
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val data_beats = Vec.tabulate(mifDataBeats) { i => UInt(i * 0x20) }
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val (r_count, r_done) = Counter(io.mem.r.fire(), mifDataBeats)
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val (w_count, w_done) = Counter(io.mem.w.fire(), mifDataBeats)
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io.mem.aw.valid := (state === s_write) && !addr_sent
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io.mem.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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len = UInt(mifDataBeats - 1),
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size = UInt(log2Up(mifDataBits / 8)))
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io.mem.w.valid := (state === s_write) && !data_sent.andR
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io.mem.w.bits := NastiWriteDataChannel(
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data = data_beats(w_count),
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last = w_count === UInt(mifDataBeats - 1))
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io.mem.ar.valid := (state === s_read)
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io.mem.ar.bits := NastiReadAddressChannel(
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id = UInt(1),
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addr = UInt(0),
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len = UInt(mifDataBeats - 1),
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size = UInt(log2Up(mifDataBits / 8)))
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io.mem.r.ready := (state === s_wait)
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io.mem.b.ready := Bool(true)
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when (state === s_start) { state := s_write }
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when (io.mem.aw.fire()) { addr_sent := Bool(true) }
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when (io.mem.w.fire()) { data_sent := data_sent | UIntToOH(w_count) }
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when (w_done) { state := s_read }
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when (io.mem.ar.fire()) { state := s_wait }
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when (r_done) { state := s_finish }
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io.finished := (state === s_finish)
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assert(!io.mem.r.valid || io.mem.r.bits.data === data_beats(r_count),
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"NASTI Block Test: results do not match")
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}
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class NastiSmallTest(implicit p: Parameters) extends NastiTest()(p) {
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val (s_start :: s_write_addr :: s_write_data ::
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s_read :: s_wait :: s_finish :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_start)
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val write_acked = Reg(init = Bool(false))
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val ref_data = UInt(0x35abffcd, mifDataBits)
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io.mem.aw.valid := (state === s_write_addr)
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io.mem.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0x20C),
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len = UInt(0),
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size = UInt("b010"))
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io.mem.w.valid := (state === s_write_data)
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io.mem.w.bits := NastiWriteDataChannel(
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data = ref_data,
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last = Bool(true))
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io.mem.ar.valid := (state === s_read)
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io.mem.ar.bits := NastiReadAddressChannel(
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id = UInt(1),
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addr = UInt(0x20C),
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len = UInt(0),
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size = UInt("b010"))
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io.mem.r.ready := (state === s_wait)
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io.mem.b.ready := Bool(true)
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when (state === s_start) { state := s_write_addr }
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when (io.mem.aw.fire()) { state := s_write_data }
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when (io.mem.w.fire()) { state := s_read }
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when (io.mem.ar.fire()) { state := s_wait }
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when (io.mem.r.fire()) { state := s_finish }
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io.finished := (state === s_finish)
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assert(!io.mem.r.valid || io.mem.r.bits.data === ref_data,
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"NASTI Small Test: results do not match")
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}
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class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p)
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with HasNastiParameters {
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disablePorts(mem = false)
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val tests = Seq(Module(new NastiBlockTest), Module(new NastiSmallTest))
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val arbiter = Module(new NastiArbiter(tests.size))
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val converter = Module(new TileLinkIONastiIOConverter()(
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p.alterPartial { case TLId => "Outermost" }))
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val widener = Module(new TileLinkIOWidener("Outermost", "L1toL2"))
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arbiter.io.master <> tests.map(_.io.mem)
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converter.io.nasti <> arbiter.io.slave
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widener.io.in <> converter.io.tl
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io.mem <> widener.io.out
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io.finished := tests.map(_.io.finished).reduce(_ && _)
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}
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