151 lines
4.2 KiB
Scala
151 lines
4.2 KiB
Scala
package groundtest
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import Chisel._
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import rocket._
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import uncore._
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import junctions.{SmiIO, ParameterizedBundle}
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import scala.util.Random
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import cde.{Parameters, Field}
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case object BuildGroundTest extends Field[(Int, Parameters) => GroundTest]
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case object GroundTestMaxXacts extends Field[Int]
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/** A "cache" that responds to probe requests with a release indicating
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* the block is not present */
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class DummyCache(implicit val p: Parameters) extends Module {
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val io = new ClientTileLinkIO
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val req = Reg(new Probe)
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val coh = ClientMetadata.onReset
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val (s_probe :: s_release :: Nil) = Enum(Bits(), 2)
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val state = Reg(init = s_probe)
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io.acquire.valid := Bool(false)
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io.probe.ready := (state === s_probe)
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io.grant.ready := Bool(true)
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io.release.valid := (state === s_release)
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io.release.bits := coh.makeRelease(req)
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when (io.probe.fire()) {
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req := io.probe.bits
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state := s_release
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}
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when (io.release.fire()) {
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state := s_probe
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}
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}
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class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val requestors = Vec(n, new TLBPTWIO).flip
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}
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val req_arb = Module(new RRArbiter(new PTWReq, n))
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req_arb.io.in <> io.requestors.map(_.req)
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req_arb.io.out.ready := Bool(true)
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def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
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class QueueChannel extends ParameterizedBundle()(p) {
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val ppn = UInt(width = ppnBits)
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val chosen = UInt(width = log2Up(n))
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}
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val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.addr)
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val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
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val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
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val s2_valid = Reg(next = req_arb.io.out.valid)
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val s2_resp = Wire(new PTWResp)
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s2_resp.pte.ppn := s2_ppn
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s2_resp.pte.reserved_for_software := UInt(0)
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s2_resp.pte.d := Bool(true)
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s2_resp.pte.r := Bool(false)
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s2_resp.pte.typ := UInt("b0101")
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s2_resp.pte.v := Bool(true)
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io.requestors.zipWithIndex.foreach { case (requestor, i) =>
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requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
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requestor.resp.bits := s2_resp
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requestor.status.vm := UInt("b01000")
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requestor.status.prv := UInt(PRV.S)
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requestor.invalidate := Bool(false)
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}
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}
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class CSRHandler(implicit val p: Parameters) extends Module {
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private val csrDataBits = 64
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private val csrAddrBits = 12
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val io = new Bundle {
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val finished = Bool(INPUT)
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val csr = new SmiIO(csrDataBits, csrAddrBits).flip
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}
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val csr_resp_valid = Reg(Bool()) // Don't reset
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val csr_resp_data = Reg(UInt(width = csrDataBits))
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io.csr.req.ready := Bool(true)
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io.csr.resp.valid := csr_resp_valid
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io.csr.resp.bits := csr_resp_data
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when (io.csr.req.fire()) {
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val req = io.csr.req.bits
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csr_resp_valid := Bool(true)
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csr_resp_data := Mux(req.addr === UInt(CSRs.mtohost), io.finished, req.data)
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}
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when (io.csr.resp.fire()) {
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csr_resp_valid := Bool(false)
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}
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}
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class GroundTestIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
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val cache = new HellaCacheIO
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val mem = new ClientUncachedTileLinkIO
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val dma = new DmaIO
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val ptw = new TLBPTWIO
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val finished = Bool(OUTPUT)
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}
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abstract class GroundTest(implicit val p: Parameters) extends Module {
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val io = new GroundTestIO
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def disablePorts(mem: Boolean = true,
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cache: Boolean = true,
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ptw: Boolean = true) {
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if (mem) {
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io.mem.acquire.valid := Bool(false)
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io.mem.grant.ready := Bool(false)
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}
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if (cache) {
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io.cache.req.valid := Bool(false)
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}
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if (ptw) {
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io.ptw.req.valid := Bool(false)
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}
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}
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}
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class GroundTestTile(id: Int, resetSignal: Bool)
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(implicit val p: Parameters) extends Tile(resetSignal)(p) {
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val test = p(BuildGroundTest)(id, dcacheParams)
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io.uncached.head <> test.io.mem
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val dcache = Module(new HellaCache()(dcacheParams))
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val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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dcacheIF.io.requestor <> test.io.cache
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dcache.io.cpu <> dcacheIF.io.cache
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io.cached.head <> dcache.io.mem
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val csr = Module(new CSRHandler)
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csr.io.finished := test.io.finished
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csr.io.csr <> io.host.csr
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val ptw = Module(new DummyPTW(2))
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ptw.io.requestors(0) <> test.io.ptw
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ptw.io.requestors(1) <> dcache.io.ptw
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}
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