| .. |
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arbiter.scala
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Don't rely on tag value for nacks
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2016-05-24 15:05:41 -07:00 |
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btb.scala
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Remove dead code from BTB
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2016-04-27 00:28:12 -07:00 |
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consts.scala
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WIP on priv spec v1.9
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2016-03-02 23:29:58 -08:00 |
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csr.scala
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Support disabling atomics extension
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2016-05-24 15:05:41 -07:00 |
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dcache.scala
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add (non-working) blocking data cache
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2016-05-20 18:59:05 -07:00 |
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decode.scala
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Use Seq, not Iterable, when traversal order matters
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2015-07-29 00:24:58 -07:00 |
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dma.scala
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get rid of unused imports
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2016-05-02 18:23:46 -07:00 |
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dpath_alu.scala
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Improve ALU QoR
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2016-01-20 17:42:31 -08:00 |
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fpu.scala
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Added Field[Int] to SFMALatency/DFMALatency params
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2016-04-06 14:50:57 -07:00 |
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frontend.scala
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Use TLB flush signal to I$ explicitly
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2016-04-22 15:41:31 -07:00 |
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icache.scala
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Separate I$ and D$ interface signals that span clock cycles
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2016-04-01 19:30:39 -07:00 |
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idecode.scala
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Support disabling atomics extension
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2016-05-24 15:05:41 -07:00 |
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instructions.scala
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ERET -> xRET; remove mcfgaddr
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2016-04-30 17:32:51 -07:00 |
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multiplier.scala
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fix more Chisel3 deprecations
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2016-01-14 14:46:31 -08:00 |
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nbdcache.scala
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IOMSHR: support atomic operations
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2016-05-24 15:00:50 -07:00 |
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package.scala
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make mtvec configurable and writeable
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2016-01-29 14:51:56 -08:00 |
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ptw.scala
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Handle invalidate_lr in cache arbiter, not tile
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2016-04-27 11:22:04 -07:00 |
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rocc.scala
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WIP on priv spec v1.9
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2016-03-02 23:29:58 -08:00 |
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rocket.scala
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Support disabling atomics extension
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2016-05-24 15:05:41 -07:00 |
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tile.scala
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Instantiate blocking D$ when NMSHRS=0
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2016-05-24 15:05:41 -07:00 |
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tlb.scala
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MPRV takes effect regardless of privilege mode
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2016-05-02 19:53:25 -07:00 |
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util.scala
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Avoid needless Vec generation
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2016-04-27 00:28:39 -07:00 |
