riscv/rocket-chip
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  • 95a2e6ef27 coreplex: improve tile attachment adapters Henry Cook 2017-10-19 19:48:20 -0700
  • 2175758050 interrupts: implement in crossing wrapper Wesley W. Terpstra 2017-10-19 22:19:19 -0700
  • c6f95570df IntNodes: moved from tilelink to their own package Wesley W. Terpstra 2017-10-19 20:44:54 -0700
  • 6bc9c9fc6c coreplex: add a crossing wrapper to generalize the island pattern Wesley W. Terpstra 2017-10-19 18:51:22 -0700
  • 7453186b59 diplomacy: add reflection for parent modules to nodes Wesley W. Terpstra 2017-10-19 18:51:00 -0700
  • c4978712c9 csr: allow for superscalar decode (#1069) Christopher Celio 2017-10-25 13:58:26 -0700
  • 897b686377 Merge pull request #1066 from freechipsproject/diplomacy_paper Megan Wachs 2017-10-23 16:52:01 -0700
  • ffffafc7c3 Add link to Diplomatic Design Patterns Paper Megan Wachs 2017-10-23 15:21:46 -0700
  • 680f3b1620 Merge pull request #1060 from freechipsproject/fix-address-format Richard Xia 2017-10-19 10:45:03 -0700
  • 82b1aa8116 coreplex: print the A first to look nicer Wesley W. Terpstra 2017-10-18 16:52:35 -0700
  • a1ac23d7ec coreplex: continue to print the device name in the address map Wesley W. Terpstra 2017-10-18 16:44:53 -0700
  • 3b36dda9e1 Merge pull request #1059 from freechipsproject/add-supports-atomics-property Richard Xia 2017-10-18 16:30:24 -0700
  • 5a951799aa Add atomics support to DTS JSON file. Richard Xia 2017-10-18 15:16:01 -0700
  • e9e05b5f3b Add a check that MaxHartIdBits is enough for all hartids (#1054) Megan Wachs 2017-10-13 15:20:35 -0700
  • 1852ccd8f3 Merge pull request #1053 from freechipsproject/resource-cacheable Henry Cook 2017-10-12 17:49:49 -0700
  • 8b58327fa4 axi4: conversion from TL does not need beatBytes (#1051) Wesley W. Terpstra 2017-10-12 16:41:54 -0700
  • 21b5367259 Expand C.UNIMP correctly (#1052) Andrew Waterman 2017-10-12 14:00:14 -0700
  • ad243ef9f5 tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so Henry Cook 2017-10-12 13:49:40 -0700
  • ad543e5bb6 Merge pull request #1050 from freechipsproject/uncacheable-tims Henry Cook 2017-10-12 13:04:00 -0700
  • f82e441426 axi4: implement a diplomatic AXI4 clock crossing (#1049) Wesley W. Terpstra 2017-10-12 00:05:45 -0700
  • 66e4bfc2d9 rocket: TIMs should never be cached Henry Cook 2017-10-11 18:22:52 -0700
  • b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params Henry Cook 2017-10-11 17:12:03 -0700
  • 024ccd8ac2 Merge pull request #1048 from freechipsproject/local_int_hookup Henry Cook 2017-10-11 17:08:24 -0700
  • 7b4c48d005 Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars Megan Wachs 2017-10-11 13:14:25 -0700
  • 60934ac622 coreplex: TilePortParams use BasicBusBlockers Henry Cook 2017-10-11 13:35:06 -0700
  • 2dbe882e58 tilelink: add BasicBusBlocker device Henry Cook 2017-10-11 13:16:50 -0700
  • 9f8e3d8879 tilelink: BusBypass can be sent to DeadlockDevice Henry Cook 2017-10-11 12:45:36 -0700
  • ec056535dc tilelink: add DeadlockDevice Henry Cook 2017-10-11 12:44:23 -0700
  • b566ffedea system: fix DefaultFPGAConfig (#1047) Wesley W. Terpstra 2017-10-11 10:48:41 -0700
  • 8e1a002c4e Merge pull request #1033 from freechipsproject/dont-touch Wesley W. Terpstra 2017-10-11 00:59:37 -0700
  • 329a5c35d4 tilelink: unsafe cache cork discards outer d.sink Henry Cook 2017-10-11 00:30:51 -0700
  • 1240cb275c coreplex: TilePortParams formatting Henry Cook 2017-10-11 00:29:11 -0700
  • 6f3a4cd733 build: pass annotations to firrtl Wesley W. Terpstra 2017-10-10 23:42:55 -0700
  • 5d62c321f4 generator: create annotation file Wesley W. Terpstra 2017-10-10 23:23:06 -0700
  • 75345b6048 rocket: don't remove ports on top module Henry Cook 2017-10-05 16:29:16 -0700
  • 5ff4c1674a Merge pull request #1044 from freechipsproject/nicer-clint Wesley W. Terpstra 2017-10-10 20:33:00 -0700
  • b3bdf5eca6 RegField: default argument for .bytes Wesley W. Terpstra 2017-10-10 19:49:19 -0700
  • e094b94ce5 clint: use RegField.toBytes to save some work Wesley W. Terpstra 2017-10-10 17:22:15 -0700
  • 10472b4296 diplomacy: auto connect bundles in a stable order (#1045) Wesley W. Terpstra 2017-10-10 19:41:46 -0700
  • 1867a5b226 rocket: only cache when AcquireT is possible Henry Cook 2017-10-10 18:06:58 -0700
  • b2bc46471b Conditionalize some covers that are sometimes impossible (#1043) Andrew Waterman 2017-10-10 17:14:33 -0700
  • ef28ce8d2f Merge pull request #1042 from freechipsproject/bump-riscv-tools Richard Xia 2017-10-10 16:31:38 -0700
  • 37406706b4 coreplex: move CacheCork in front of SBus Henry Cook 2017-10-10 16:24:32 -0700
  • 8f5f80f958 coreplex: TileSlavePortParams inject adapters into PBus Henry Cook 2017-10-10 15:25:08 -0700
  • 660355004e coreplex: TileMasterPortParams inject adapters into SBus Henry Cook 2017-10-10 15:02:50 -0700
  • 167aa7b793 Bump riscv-tools. Richard Xia 2017-10-10 14:14:10 -0700
  • 50429daef4 Merge pull request #1036 from freechipsproject/l1-cover Andrew Waterman 2017-10-10 12:28:48 -0700
  • 9026646459 coreplex: first cut at using RocketCrossingParams Henry Cook 2017-10-09 23:43:18 -0700
  • d6766a8c68 RocketTile: make sure 'hartid' is available for traits (#1037) Wesley W. Terpstra 2017-10-09 21:03:18 -0700
  • a9686ab883 Merge pull request #1035 from freechipsproject/big-paddr Andrew Waterman 2017-10-09 20:59:21 -0700
  • 1474ab438d Remove extraneous signal Andrew Waterman 2017-10-09 18:33:50 -0700
  • f3825270c1 Add some covers for L1 memory system Andrew Waterman 2017-10-09 18:33:36 -0700
  • 2c4009a138 Fix paddrBits < xLen && paddrBits == vaddrBits case Andrew Waterman 2017-10-09 16:48:04 -0700
  • 0e6aa7ae9d Merge pull request #1024 from freechipsproject/jtag_coverage Megan Wachs 2017-10-09 12:29:18 -0700
  • d78ad857ee Merge pull request #1034 from freechipsproject/base-tile Andrew Waterman 2017-10-09 11:42:20 -0700
  • 0916cf1bdd JTAG Coverage: Correct jtag_reset case Megan Wachs 2017-10-09 09:54:15 -0700
  • 9efe1c448e Merge remote-tracking branch 'origin/master' into HEAD Megan Wachs 2017-10-09 09:48:38 -0700
  • 986cbfb6b1 For Rockets without VM, widen vaddrBits to paddrBits Andrew Waterman 2017-10-07 17:33:36 -0700
  • a0e5a20b60 Don't route branch comparison result through ALU output mux Andrew Waterman 2017-10-07 17:31:23 -0700
  • 36c39d01e4 Factor out most of HasRocketTiles into HasTiles Andrew Waterman 2017-10-07 17:29:50 -0700
  • 70a4127cb8 Factor out some of HaveRocketTiles into HaveTiles Andrew Waterman 2017-10-06 00:56:23 -0700
  • 34e96c03b1 Move HCF to BaseTile Andrew Waterman 2017-10-05 23:49:35 -0700
  • 71205b70cc Make RocketTileWrapper a BaseTile Andrew Waterman 2017-10-05 22:46:16 -0700
  • 4645b61fd3 Decouple BaseTile from HasTileLinkMasterPort Andrew Waterman 2017-10-05 22:23:58 -0700
  • 86a1953287 Merge pull request #1032 from freechipsproject/fpga_pipeline_fpu_master Andrew Waterman 2017-10-05 20:11:34 -0700
  • 5498468743 FPU : simplify pipeline register generation in FMA Henry Styles 2017-09-29 15:40:39 -0700
  • 7a46715cbc FPU : to assist retiming move upto first 2 register stages of into FMA Henry Styles 2017-09-28 18:34:28 -0700
  • bd045a3b95 tilelink: split Acquire into Acquire{Block,Perm} (#1030) Wesley W. Terpstra 2017-10-05 12:49:49 -0700
  • 81b9ac42a3 add comments to diplomacy resource. (#913) Wei Song (宋威) 2017-10-05 20:45:56 +0100
  • 9040d921b5 Merge pull request #1031 from freechipsproject/non-contiguous-hartids Henry Cook 2017-10-05 12:44:31 -0700
  • 8da7aabd51 tile: supply hartid from RocketTileParams Henry Cook 2017-10-05 00:31:53 -0700
  • 45581e60f0 Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid" Henry Cook 2017-10-05 00:26:44 -0700
  • 5a84564203 Merge pull request #1023 from freechipsproject/csr-cleanup Andrew Waterman 2017-10-04 14:04:59 -0700
  • 32fda51a2c Get rid of paddrBits from SystemBus (#1029) Andrew Waterman 2017-10-04 12:11:37 -0700
  • 7bcf28c585 Define fetchBytes in HasCoreParams, not Frontend Andrew Waterman 2017-09-29 12:31:26 -0700
  • 2786e42d99 Don't register interrupts in CSRFile Andrew Waterman 2017-09-29 12:30:32 -0700
  • 5cfe070932 Add option to make misa read-only Andrew Waterman 2017-09-20 19:16:34 -0700
  • 09468a272b Add option to remove basic counters (mcycle/minstret) Andrew Waterman 2017-09-20 19:15:36 -0700
  • ab0821f25b Move microarchitecture-neutral params from Rocket to Core Andrew Waterman 2017-09-20 14:04:13 -0700
  • 190d5c50d9 Remove deprecated custom-CSR support Andrew Waterman 2017-09-20 13:43:25 -0700
  • 5232a29d7d Merge pull request #1027 from freechipsproject/dont-touch-hartid Henry Cook 2017-10-03 12:55:34 -0700
  • d33737802a util: add DontTouch trait with dontTouchPorts method Henry Cook 2017-10-02 19:34:51 -0700
  • aa3a18222c HellaCache: users like to peep resp.data and resp.addr Henry Cook 2017-10-02 19:01:05 -0700
  • cedfb0e784 coreplex: dontTouch the rocket_tile_inputs wire Henry Cook 2017-10-02 17:41:52 -0700
  • a2dc13669a Error grants (#1025) Wesley W. Terpstra 2017-10-02 14:49:25 -0700
  • 9c9cb68462 JTAG Coverage: Add reset coverage points Megan Wachs 2017-10-02 11:07:55 -0700
  • a8ab06d572 JTAG: Add coverage points to the JTAG Tap Megan Wachs 2017-10-02 11:05:45 -0700
  • 723af5e6b6 Merge pull request #971 from freechipsproject/bump-chisel-firrtl Jack Koenig 2017-09-29 17:24:12 -0700
  • 8891bf1b64 Bump chisel3 and firrtl, update plugin versions Jack Koenig 2017-08-23 13:33:22 -0700
  • 547bdc2b5b diplomacy: standardize sram device resource naming (#1022) Henry Cook 2017-09-29 14:52:26 -0700
  • 9137f54f59 Merge pull request #1020 from freechipsproject/fix-trace-insn Andrew Waterman 2017-09-27 18:47:24 -0700
  • e315a7aaa7 Merge pull request #993 from freechipsproject/auto-diplomacy-bundles Wesley W. Terpstra 2017-09-27 17:39:53 -0700
  • 9eaf50762e Don't report exceptions as valid instructions in the printed log Andrew Waterman 2017-09-27 16:29:42 -0700
  • 0a287df0f7 Merge remote-tracking branch 'origin/master' into auto-diplomacy-bundles Wesley W. Terpstra 2017-09-27 16:28:10 -0700
  • 31c5246446 Provide correct trace insn on interrupts when possible Andrew Waterman 2017-09-27 16:27:53 -0700
  • 33b46af806 Merge pull request #1007 from freechipsproject/tl-error Henry Cook 2017-09-27 16:22:32 -0700
  • feae216f05 clint: output interrupts in the correct direction Wesley W. Terpstra 2017-09-27 15:18:42 -0700
  • 05112b49a3 Merge branch 'master' into tl-error Henry Cook 2017-09-27 14:50:17 -0700
  • 652d57291c Merge pull request #1018 from freechipsproject/refine-trace-port Henry Cook 2017-09-27 14:46:27 -0700
  • 5d08b37dab Merge pull request #1019 from freechipsproject/move-rocket-int-sync Henry Cook 2017-09-27 14:46:02 -0700