Merge pull request #1034 from freechipsproject/base-tile
Generalize Tile/Coreplex hierarchy
This commit is contained in:
commit
d78ad857ee
@ -6,6 +6,9 @@ import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.tile.{BaseTile, TileParams, SharedMemoryTLEdge, HasExternallyDrivenTileConstants}
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
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import freechips.rocketchip.util._
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/** Enumerates the three types of clock crossing between tiles and system bus */
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@ -29,6 +32,21 @@ abstract class BareCoreplexModule[+L <: BareCoreplex](_outer: L) extends LazyMod
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println(outer.dts)
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}
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trait HasTiles extends HasSystemBus {
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protected def tileParams: Seq[TileParams]
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def nRocketTiles = tileParams.size
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def hartIdList = tileParams.map(_.hartid)
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// Handle interrupts to be routed directly into each tile
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// TODO: figure out how to merge the localIntNodes and coreIntXbar
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def localIntCounts = tileParams.map(_.core.nLocalInterrupts)
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def localIntNodes = tileParams map { t =>
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(t.core.nLocalInterrupts > 0).option(LazyModule(new IntXbar).intnode)
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}
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val tiles: Seq[BaseTile]
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}
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/** Base Coreplex class with no peripheral devices or ports added */
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abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
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with HasInterruptBus
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@ -87,6 +105,46 @@ abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
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}
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}
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class ClockedTileInputs(implicit val p: Parameters) extends ParameterizedBundle
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with HasExternallyDrivenTileConstants
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with Clocked
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trait HasTilesBundle {
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val tile_inputs: Vec[ClockedTileInputs]
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}
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trait HasTilesModuleImp extends LazyModuleImp
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with HasTilesBundle
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with HasResetVectorWire {
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val outer: HasTiles
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def resetVectorBits: Int = {
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// Consider using the minimum over all widths, rather than enforcing homogeneity
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val vectors = outer.tiles.map(_.module.io.reset_vector)
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require(vectors.tail.forall(_.getWidth == vectors.head.getWidth))
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vectors.head.getWidth
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}
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val tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedTileInputs()(p.alterPartial {
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case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
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})))
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// Unconditionally wire up the non-diplomatic tile inputs
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outer.tiles.map(_.module).zip(tile_inputs).foreach { case(tile, wire) =>
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tile.clock := wire.clock
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tile.reset := wire.reset
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tile.io.hartid := wire.hartid
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tile.io.reset_vector := wire.reset_vector
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}
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// Default values for tile inputs; may be overriden in other traits
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tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
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wire.clock := clock
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wire.reset := reset
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wire.hartid := UInt(i)
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wire.reset_vector := global_reset_vector
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}
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}
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abstract class BaseCoreplexModule[+L <: BaseCoreplex](_outer: L) extends BareCoreplexModule(_outer) {
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println("Generated Address Map")
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private val aw = (outer.sharedMemoryTLEdge.bundle.addressBits-1)/4 + 1
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@ -14,7 +14,7 @@ import freechips.rocketchip.util._
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case object RocketTilesKey extends Field[Seq[RocketTileParams]](Nil)
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case object RocketCrossing extends Field[CoreplexClockCrossing](SynchronousCrossing())
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trait HasRocketTiles extends HasSystemBus
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trait HasRocketTiles extends HasTiles
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with HasPeripheryBus
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with HasPeripheryPLIC
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with HasPeripheryClint
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@ -22,21 +22,11 @@ trait HasRocketTiles extends HasSystemBus
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val module: HasRocketTilesModuleImp
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private val crossing = p(RocketCrossing)
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private val tileParams = p(RocketTilesKey)
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val nRocketTiles = tileParams.size
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val hartIdList = tileParams.map(_.hartid)
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// Handle interrupts to be routed directly into each tile
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// TODO: figure out how to merge the localIntNodes and coreIntXbar below
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val localIntCounts = tileParams.map(_.core.nLocalInterrupts)
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val localIntNodes = tileParams map { t =>
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(t.core.nLocalInterrupts > 0).option(LazyModule(new IntXbar).intnode)
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}
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protected val tileParams = p(RocketTilesKey)
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// Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
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// according to the specified type of clock crossing.
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val wiringTuple = localIntNodes.zip(tileParams)
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val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case (lip, tp) =>
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val tiles: Seq[BaseTile] = localIntNodes.zip(tileParams).map { case (lip, tp) =>
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val pWithExtra = p.alterPartial {
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case TileKey => tp
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case BuildRoCC => tp.rocc
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@ -95,45 +85,9 @@ trait HasRocketTiles extends HasSystemBus
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}
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}
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class ClockedRocketTileInputs(implicit val p: Parameters) extends ParameterizedBundle
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with HasExternallyDrivenTileConstants
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with Clocked
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trait HasRocketTilesBundle {
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val rocket_tile_inputs: Vec[ClockedRocketTileInputs]
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}
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trait HasRocketTilesModuleImp extends LazyModuleImp
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with HasRocketTilesBundle
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with HasResetVectorWire
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trait HasRocketTilesModuleImp extends HasTilesModuleImp
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with HasPeripheryDebugModuleImp {
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val outer: HasRocketTiles
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def resetVectorBits: Int = {
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// Consider using the minimum over all widths, rather than enforcing homogeneity
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val vectors = outer.rocket_tiles.map(_.module.io.reset_vector)
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require(vectors.tail.forall(_.getWidth == vectors.head.getWidth))
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vectors.head.getWidth
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}
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val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial {
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case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
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})))
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// Unconditionally wire up the non-diplomatic tile inputs
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outer.rocket_tiles.map(_.module).zip(rocket_tile_inputs).foreach { case(tile, wire) =>
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tile.clock := wire.clock
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tile.reset := wire.reset
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tile.io.hartid := wire.hartid
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tile.io.reset_vector := wire.reset_vector
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}
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// Default values for tile inputs; may be overriden in other traits
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rocket_tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
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wire.clock := clock
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wire.reset := reset
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wire.hartid := UInt(i)
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wire.reset_vector := global_reset_vector
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}
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}
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class RocketCoreplex(implicit p: Parameters) extends BaseCoreplex
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@ -25,7 +25,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
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})
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)}
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tiles.foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.masterNode }
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tiles.flatMap(_.dcacheOpt).foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.node }
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val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes))
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pbusRAM.node := pbus.toVariableWidthSlaves
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@ -31,13 +31,13 @@ case object GroundTestTilesKey extends Field[Seq[GroundTestTileParams]]
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abstract class GroundTestTile(params: GroundTestTileParams)(implicit p: Parameters) extends BaseTile(params)(p) {
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val slave = None
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val dcacheOpt = params.dcache.map { dc => LazyModule(HellaCache(0, dc.nMSHRs == 0)) }
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dcacheOpt.foreach { tileBus.node := _.node }
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override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this))
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}
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class GroundTestTileBundle[+L <: GroundTestTile](_outer: L) extends BaseTileBundle(_outer) {
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val status = new GroundTestStatus
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val halt_and_catch_fire = None
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}
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class GroundTestTileModule[+L <: GroundTestTile, +B <: GroundTestTileBundle[L]](_outer: L, _io: () => B) extends BaseTileModule(_outer, _io) {
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@ -65,6 +65,7 @@ case class TraceGenParams(
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memStart: BigInt, //p(ExtMem).base
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numGens: Int) extends GroundTestTileParams {
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def build(i: Int, p: Parameters): GroundTestTile = new TraceGenTile(i, this)(p)
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val hartid = 0
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val trace = false
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}
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@ -38,7 +38,7 @@ object ALU
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def isMulFN(fn: UInt, cmp: UInt) = fn(1,0) === cmp(1,0)
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def isSub(cmd: UInt) = cmd(3)
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def isCmp(cmd: UInt) = cmd === FN_SEQ || cmd === FN_SNE || cmd >= FN_SLT
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def isCmp(cmd: UInt) = cmd >= FN_SLT
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def cmpUnsigned(cmd: UInt) = cmd(1)
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def cmpInverted(cmd: UInt) = cmd(0)
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def cmpEq(cmd: UInt) = !cmd(3)
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@ -64,10 +64,10 @@ class ALU(implicit p: Parameters) extends CoreModule()(p) {
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io.adder_out := io.in1 + in2_inv + isSub(io.fn)
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// SLT, SLTU
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io.cmp_out := cmpInverted(io.fn) ^
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Mux(cmpEq(io.fn), in1_xor_in2 === UInt(0),
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val slt =
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Mux(io.in1(xLen-1) === io.in2(xLen-1), io.adder_out(xLen-1),
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Mux(cmpUnsigned(io.fn), io.in2(xLen-1), io.in1(xLen-1))))
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Mux(cmpUnsigned(io.fn), io.in2(xLen-1), io.in1(xLen-1)))
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io.cmp_out := cmpInverted(io.fn) ^ Mux(cmpEq(io.fn), in1_xor_in2 === UInt(0), slt)
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// SLL, SRL, SRA
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val (shamt, shin_r) =
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@ -88,7 +88,7 @@ class ALU(implicit p: Parameters) extends CoreModule()(p) {
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// AND, OR, XOR
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val logic = Mux(io.fn === FN_XOR || io.fn === FN_OR, in1_xor_in2, UInt(0)) |
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Mux(io.fn === FN_OR || io.fn === FN_AND, io.in1 & io.in2, UInt(0))
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val shift_logic = (isCmp(io.fn) && io.cmp_out) | logic | shout
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val shift_logic = (isCmp(io.fn) && slt) | logic | shout
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val out = Mux(io.fn === FN_ADD || io.fn === FN_SUB, io.adder_out, shift_logic)
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io.out := out
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@ -84,9 +84,6 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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val r_req = Reg(new PTWReq)
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val r_req_dest = Reg(Bits())
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val r_pte = Reg(new PTE)
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val vpn_idxs = (0 until pgLevels).map(i => (r_req.addr >> (pgLevels-i-1)*pgLevelBits)(pgLevelBits-1,0))
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val vpn_idx = vpn_idxs(count)
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val arb = Module(new RRArbiter(new PTWReq, n))
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arb.io.in <> io.requestor.map(_.req)
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@ -104,7 +101,11 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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(res, (tmp.ppn >> ppnBits) =/= 0)
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}
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val traverse = pte.table() && !invalid_paddr && count < pgLevels-1
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val pte_addr = Cat(r_pte.ppn, vpn_idx) << log2Ceil(xLen/8)
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val pte_addr = if (!usingVM) 0.U else {
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val vpn_idxs = (0 until pgLevels).map(i => (r_req.addr >> (pgLevels-i-1)*pgLevelBits)(pgLevelBits-1,0))
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val vpn_idx = vpn_idxs(count)
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Cat(r_pte.ppn, vpn_idx) << log2Ceil(xLen/8)
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}
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when (arb.io.out.fire()) {
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r_req := arb.io.out.bits
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@ -152,6 +152,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val mem_reg_raw_inst = Reg(UInt())
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val mem_reg_wdata = Reg(Bits())
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val mem_reg_rs2 = Reg(Bits())
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val mem_br_taken = Reg(Bool())
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val take_pc_mem = Wire(Bool())
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val wb_reg_valid = Reg(Bool())
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@ -361,7 +362,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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// memory stage
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val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt
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val mem_br_taken = mem_reg_wdata(0)
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val mem_br_target = mem_reg_pc.asSInt +
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Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
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Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst),
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@ -403,6 +403,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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mem_reg_raw_inst := ex_reg_raw_inst
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mem_reg_pc := ex_reg_pc
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mem_reg_wdata := alu.io.out
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mem_br_taken := alu.io.cmp_out
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when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) {
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val typ = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_ctrl.mem_type)
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@ -97,7 +97,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
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val vm_enabled = Bool(usingVM) && io.ptw.ptbr.mode(io.ptw.ptbr.mode.getWidth-1) && priv_uses_vm && !io.req.bits.passthrough
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// share a single physical memory attribute checker (unshare if critical path)
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val (vpn, pgOffset) = Split(io.req.bits.vaddr, pgIdxBits)
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val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits)
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val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
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val do_refill = Bool(usingVM) && io.ptw.resp.valid
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val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate)
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@ -121,8 +121,8 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
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val prot_x = fastCheck(_.executable) && pmp.io.x
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val prot_eff = fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType)
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val lookup_tag = Cat(io.ptw.ptbr.asid, vpn(vpnBits-1,0))
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val hitsVec = (0 until totalEntries).map { i => vm_enabled && {
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val lookup_tag = Cat(io.ptw.ptbr.asid, vpn)
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val hitsVec = (0 until totalEntries).map { i => if (!usingVM) false.B else vm_enabled && {
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var tagMatch = valid(i)
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for (j <- 0 until pgLevels) {
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val base = vpnBits - (j + 1) * pgLevelBits
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@ -133,7 +133,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
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val hits = hitsVec.asUInt
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val level = Mux1H(hitsVec.init, entries.map(_.level))
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val partialPPN = Mux1H(hitsVec.init, entries.map(_.ppn))
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val ppn = {
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val ppn = if (!usingVM) vpn else {
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var ppn = Mux(vm_enabled, partialPPN, vpn)(pgLevelBits*pgLevels - 1, pgLevelBits*(pgLevels - 1))
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for (i <- 1 until pgLevels)
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ppn = Cat(ppn, (Mux(level < i, vpn, 0.U) | partialPPN)(vpnBits - i*pgLevelBits - 1, vpnBits - (i + 1)*pgLevelBits))
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@ -187,7 +187,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
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val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1)).orR
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val bad_va = vm_enabled &&
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(if (vpnBits == vpnBitsExtended) Bool(false)
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else vpn(vpnBits) =/= vpn(vpnBits-1))
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else (io.req.bits.vaddr.asSInt < 0.S) =/= (vpn.asSInt < 0.S))
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val lrscAllowed = Mux(Bool(usingDataScratchpad), 0.U, c_array)
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val ae_array =
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@ -230,7 +230,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
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io.resp.cacheable := (c_array & hits).orR
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io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint)
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io.resp.miss := do_refill || tlb_miss || multipleHits
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io.resp.paddr := Cat(ppn, pgOffset)
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io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
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io.ptw.req.valid := state === s_request
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io.ptw.req.bits <> io.ptw.status
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@ -256,7 +256,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
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}
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when (sfence) {
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assert((io.req.bits.sfence.bits.addr >> pgIdxBits) === vpn(vpnBits-1,0))
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assert((io.req.bits.sfence.bits.addr >> pgIdxBits) === vpn)
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valid := Mux(io.req.bits.sfence.bits.rs1, valid & ~hits(totalEntries-1, 0),
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Mux(io.req.bits.sfence.bits.rs2, valid & entries.map(_.g).asUInt, 0))
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}
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@ -22,6 +22,7 @@ trait TileParams {
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val rocc: Seq[RoCCParams]
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val btb: Option[BTBParams]
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val trace: Boolean
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val hartid: Int
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}
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trait HasTileParameters {
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@ -41,7 +42,14 @@ trait HasTileParameters {
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def iLen: Int = 32
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def pgIdxBits: Int = 12
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def pgLevelBits: Int = 10 - log2Ceil(xLen / 32)
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def vaddrBits: Int = pgIdxBits + pgLevels * pgLevelBits
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def vaddrBits: Int =
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if (usingVM) {
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val v = pgIdxBits + pgLevels * pgLevelBits
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require(v == xLen || xLen > v && v > paddrBits)
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v
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} else {
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paddrBits min xLen
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}
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def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits
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def vpnBits: Int = vaddrBits - pgIdxBits
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def ppnBits: Int = paddrBits - pgIdxBits
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@ -52,7 +60,7 @@ trait HasTileParameters {
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def maxPAddrBits: Int = xLen match { case 32 => 34; case 64 => 56 }
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def hartIdLen: Int = p(MaxHartIdBits)
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def resetVectorLen: Int = paddrBits min vaddrBitsExtended
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def resetVectorLen: Int = paddrBits
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def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
|
||||
}
|
||||
@ -99,19 +107,17 @@ trait CanHaveInstructionTracePort extends Bundle with HasTileParameters {
|
||||
|
||||
/** Base class for all Tiles that use TileLink */
|
||||
abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
|
||||
with HasTileParameters
|
||||
with HasTileLinkMasterPort {
|
||||
override lazy val module = new BaseTileModule(this, () => new BaseTileBundle(this))
|
||||
with HasTileParameters {
|
||||
def module: BaseTileModule[BaseTile, BaseTileBundle[BaseTile]]
|
||||
}
|
||||
|
||||
class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
|
||||
with HasTileLinkMasterPortBundle
|
||||
abstract class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
|
||||
with HasExternallyDrivenTileConstants
|
||||
with CanHaveInstructionTracePort
|
||||
with CanHaltAndCatchFire
|
||||
|
||||
class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
|
||||
with HasTileParameters
|
||||
with HasTileLinkMasterPortModule {
|
||||
with HasTileParameters {
|
||||
require(xLen == 32 || xLen == 64)
|
||||
require(paddrBits <= maxPAddrBits)
|
||||
require(resetVectorLen <= xLen)
|
||||
|
@ -181,7 +181,12 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
|
||||
ptw.io.requestor <> ptwPorts
|
||||
}
|
||||
|
||||
abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends LazyModule {
|
||||
class RocketTileWrapperBundle[+L <: RocketTileWrapper](_outer: L) extends BaseTileBundle(_outer)
|
||||
with CanHaltAndCatchFire {
|
||||
val halt_and_catch_fire = _outer.rocket.module.io.halt_and_catch_fire.map(_.cloneType)
|
||||
}
|
||||
|
||||
abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends BaseTile(rtp) {
|
||||
val rocket = LazyModule(new RocketTile(rtp))
|
||||
val asyncIntNode : IntInwardNode
|
||||
val periphIntNode : IntInwardNode
|
||||
@ -213,13 +218,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters)
|
||||
|
||||
def outputInterruptXingLatency: Int
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = IO(new CoreBundle
|
||||
with HasExternallyDrivenTileConstants
|
||||
with CanHaveInstructionTracePort
|
||||
with CanHaltAndCatchFire {
|
||||
val halt_and_catch_fire = rocket.module.io.halt_and_catch_fire.map(_.cloneType)
|
||||
})
|
||||
override lazy val module = new BaseTileModule(this, () => new RocketTileWrapperBundle(this)) {
|
||||
// signals that do not change based on crossing type:
|
||||
rocket.module.io.hartid := io.hartid
|
||||
rocket.module.io.reset_vector := io.reset_vector
|
||||
|
Loading…
Reference in New Issue
Block a user