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Merge pull request #1033 from freechipsproject/dont-touch

Use chisel3.experimental.dontTouch (take 2)
This commit is contained in:
Wesley W. Terpstra 2017-10-11 00:59:37 -07:00 committed by GitHub
commit 8e1a002c4e
9 changed files with 33 additions and 2 deletions

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@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
%.v %.conf: %.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf -faf $*.anno -ffaaf
$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN)
cd $(generated_dir) && \

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@ -7,6 +7,7 @@ import freechips.rocketchip.util.GeneratorApp
object Generator extends GeneratorApp {
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateAnno
generateTestSuiteMakefrags // TODO: Needed only for legacy make targets
generateArtefacts
}

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@ -6,6 +6,7 @@ import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util.DontTouch
/** Example Top with periphery devices and ports, and a Rocket coreplex */
class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex
@ -25,3 +26,4 @@ class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends Ro
with HasMasterAXI4MMIOPortModuleImp
with HasSlaveAXI4PortModuleImp
with HasPeripheryBootROMModuleImp
with DontTouch

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@ -87,6 +87,7 @@ object Generator extends GeneratorApp {
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateAnno
generateTestSuiteMakefrags
generateROMs
generateArtefacts

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@ -14,6 +14,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
val dut = Module(LazyModule(new ExampleRocketSystem).module)
dut.reset := reset | dut.debug.ndreset
dut.dontTouchPorts()
dut.tieOffInterrupts()
dut.connectSimAXIMem()
dut.connectSimAXIMMIO()

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@ -5,6 +5,7 @@ package freechips.rocketchip.unittest
object Generator extends freechips.rocketchip.util.GeneratorApp {
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateAnno
generateTestSuiteMakefrags // TODO: Needed only for legacy make targets
generateArtefacts
}

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@ -10,6 +10,8 @@ import freechips.rocketchip.system.{TestGeneration, DefaultTestSuites}
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy.LazyModule
import java.io.{File, FileWriter}
import net.jcazevedo.moultingyaml._
import firrtl.annotations.AnnotationYamlProtocol._
/** Representation of the information this Generator needs to collect from external sources. */
case class ParsedInputNames(
@ -106,6 +108,13 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
}
def generateAnno {
val annotationFile = new File(td, s"$longName.anno")
val af = new FileWriter(annotationFile)
af.write(circuit.annotations.toArray.toYaml.prettyPrint)
af.close()
}
/** Output software test Makefrags, which provide targets for integration testing. */
def generateTestSuiteMakefrags {
addTestSuites

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@ -4,6 +4,7 @@
package freechips.rocketchip.util
import Chisel._
import chisel3.experimental.{dontTouch, RawModule}
import freechips.rocketchip.config.Parameters
import scala.math._
@ -21,6 +22,21 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle {
}
}
// TODO: replace this with an implicit class when @chisel unprotects dontTouchPorts
trait DontTouch {
self: RawModule =>
/** Marks every port as don't touch
*
* @note This method can only be called after the Module has been fully constructed
* (after Module(...))
*/
def dontTouchPorts(): this.type = {
self.getModulePorts.foreach(dontTouch(_))
self
}
}
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()

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@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)
$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf
$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf -faf $(generated_dir)/$*.anno -ffaaf
$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
cd $(generated_dir) && \