Merge pull request #1033 from freechipsproject/dont-touch
Use chisel3.experimental.dontTouch (take 2)
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commit
8e1a002c4e
@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
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%.v %.conf: %.fir $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf
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$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf -faf $*.anno -ffaaf
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$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN)
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cd $(generated_dir) && \
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@ -7,6 +7,7 @@ import freechips.rocketchip.util.GeneratorApp
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object Generator extends GeneratorApp {
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val longName = names.topModuleProject + "." + names.configs
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generateFirrtl
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generateAnno
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generateTestSuiteMakefrags // TODO: Needed only for legacy make targets
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generateArtefacts
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}
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@ -6,6 +6,7 @@ import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.util.DontTouch
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/** Example Top with periphery devices and ports, and a Rocket coreplex */
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class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex
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@ -25,3 +26,4 @@ class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends Ro
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with HasMasterAXI4MMIOPortModuleImp
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with HasSlaveAXI4PortModuleImp
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with HasPeripheryBootROMModuleImp
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with DontTouch
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@ -87,6 +87,7 @@ object Generator extends GeneratorApp {
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val longName = names.topModuleProject + "." + names.configs
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generateFirrtl
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generateAnno
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generateTestSuiteMakefrags
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generateROMs
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generateArtefacts
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@ -14,6 +14,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
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val dut = Module(LazyModule(new ExampleRocketSystem).module)
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dut.reset := reset | dut.debug.ndreset
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dut.dontTouchPorts()
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dut.tieOffInterrupts()
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dut.connectSimAXIMem()
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dut.connectSimAXIMMIO()
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@ -5,6 +5,7 @@ package freechips.rocketchip.unittest
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object Generator extends freechips.rocketchip.util.GeneratorApp {
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val longName = names.topModuleProject + "." + names.configs
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generateFirrtl
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generateAnno
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generateTestSuiteMakefrags // TODO: Needed only for legacy make targets
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generateArtefacts
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}
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@ -10,6 +10,8 @@ import freechips.rocketchip.system.{TestGeneration, DefaultTestSuites}
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy.LazyModule
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import java.io.{File, FileWriter}
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import net.jcazevedo.moultingyaml._
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import firrtl.annotations.AnnotationYamlProtocol._
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/** Representation of the information this Generator needs to collect from external sources. */
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case class ParsedInputNames(
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@ -106,6 +108,13 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
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Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
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}
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def generateAnno {
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val annotationFile = new File(td, s"$longName.anno")
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val af = new FileWriter(annotationFile)
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af.write(circuit.annotations.toArray.toYaml.prettyPrint)
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af.close()
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}
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/** Output software test Makefrags, which provide targets for integration testing. */
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def generateTestSuiteMakefrags {
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addTestSuites
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@ -4,6 +4,7 @@
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package freechips.rocketchip.util
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import Chisel._
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import chisel3.experimental.{dontTouch, RawModule}
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import freechips.rocketchip.config.Parameters
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import scala.math._
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@ -21,6 +22,21 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle {
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}
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}
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// TODO: replace this with an implicit class when @chisel unprotects dontTouchPorts
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trait DontTouch {
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self: RawModule =>
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/** Marks every port as don't touch
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*
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* @note This method can only be called after the Module has been fully constructed
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* (after Module(...))
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*/
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def dontTouchPorts(): this.type = {
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self.getModulePorts.foreach(dontTouch(_))
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self
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}
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}
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trait Clocked extends Bundle {
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val clock = Clock()
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val reset = Bool()
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@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
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$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf
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$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf -faf $(generated_dir)/$*.anno -ffaaf
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$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
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cd $(generated_dir) && \
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