riscv/rocket-chip
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  • 5b339b6bbd tilelink2 Monitor: catch incorrect use of source ID Wesley W. Terpstra 2017-03-27 15:24:03 -07:00
  • 75eba294ec DCache: Release from the correct ID as well Wesley W. Terpstra 2017-03-27 15:21:08 -07:00
  • 4959771c97 Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N" Wesley W. Terpstra 2017-03-27 15:19:16 -07:00
  • fa7ead6357 Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO" Wesley W. Terpstra 2017-03-27 15:19:05 -07:00
  • 861651587b debug: Update Makefile to use new OpenOCD and allow for easier debugging. (#619) Megan Wachs 2017-03-27 15:52:04 -07:00
  • 7014263c29 Update LICENSE.SiFive (#618) Megan Wachs 2017-03-27 14:55:28 -07:00
  • 70fa10fc55 Util: Add ResetCatchAndSync for synchronous deassert of Async Reset (#615) Megan Wachs 2017-03-27 03:29:07 -07:00
  • 08c4f7cea6 RocketTile: Create a wrapper for SyncRocketTile as well (#616) Megan Wachs 2017-03-27 02:45:37 -07:00
  • 722b0d521f bootrom: also setup SBI a0+a1 for when we hang (#617) Wesley W. Terpstra 2017-03-27 00:01:05 -07:00
  • 11507ac7d6 TLROM: Use Resource as a parameter rather than assuming SimpleDevice. Megan Wachs 2017-03-26 18:43:24 -07:00
  • bf648514e3 TLROM: allow name and compatibility strings to be provided by subclasses. Megan Wachs 2017-03-16 16:06:30 -07:00
  • 8e6beb80be Add ucb-art/chisel-jtag (#612) Megan Wachs 2017-03-26 18:03:21 -07:00
  • 0e2b780089 Bump hardfloat, giving us the 5th rounding mode finally! Andrew Waterman 2017-03-26 12:27:43 -07:00
  • e710e32f10 Implement new FP encoding proposal Andrew Waterman 2017-03-26 11:32:26 -07:00
  • 7180352067 Fix groundtest to provide missing signals to TLB Andrew Waterman 2017-03-26 11:30:11 -07:00
  • 5d1165c850 Express PMP mask generator using a carry chain Andrew Waterman 2017-03-26 11:12:41 -07:00
  • bb42f3bf3b WIP on FPU subword recoding Andrew Waterman 2017-03-25 15:41:43 -07:00
  • 986e1754be Merge pull request #611 from ucb-bar/expose-back-side-bus Wesley W. Terpstra 2017-03-24 23:32:50 -07:00
  • 537274b645 coreplex: move buffers inside the coreplex Wesley W. Terpstra 2017-03-24 22:53:46 -07:00
  • 5bbb75e078 rename l2FrontendBus as fsb, expose bsb Yunsup Lee 2017-03-24 21:37:47 -07:00
  • 996a31364a rocket: remove hard-coded paddrBits (#610) Henry Cook 2017-03-24 22:30:18 -07:00
  • 19485a9861 Merge pull request #609 from ucb-bar/dtb-rom Wesley W. Terpstra 2017-03-24 21:54:13 -07:00
  • e74226564c travis: add dependency on device-tree-compiler Wesley W. Terpstra 2017-03-24 20:59:33 -07:00
  • f36b1766f8 TLROM: use the smallest ROM implementation that works Wesley W. Terpstra 2017-03-24 16:07:59 -07:00
  • ac205ca10a bootrom: move to 0x10000 for more space (DTB on multicore is big) Wesley W. Terpstra 2017-03-24 16:00:00 -07:00
  • 34f8ce653a bootrom: follow SBI (a0=hartid, a1=dtb) Wesley W. Terpstra 2017-03-24 15:55:57 -07:00
  • 9a2f0d01a1 GenerateBootROM: use compiled DTB Wesley W. Terpstra 2017-03-24 14:35:11 -07:00
  • 17b1ee3037 Default to 8 PMPs; support 0 PMPs Andrew Waterman 2017-03-24 15:55:51 -07:00
  • 97006ab396 Don't modulate PMP privilege on passsthrough when !usingVM Andrew Waterman 2017-03-24 13:01:47 -07:00
  • 3f0d2fe826 Instantiate PTW unconditionally Andrew Waterman 2017-03-24 13:00:47 -07:00
  • 30415215b8 Don't check for exceptions on ScratchpadSlavePort accesses Andrew Waterman 2017-03-23 23:43:19 -07:00
  • ccd5bc9a91 Improve QoR of PMP homogeneity checker Andrew Waterman 2017-03-23 18:02:13 -07:00
  • 0182b6ca07 bump tools Andrew Waterman 2017-03-23 13:40:45 -07:00
  • e9cadf29d2 Improve DCache MMIO QoR Andrew Waterman 2017-03-23 13:18:32 -07:00
  • fb6498f2c3 Use Reg(Vec) instead of Seq(Reg) for DCache MMIO Andrew Waterman 2017-03-23 13:17:54 -07:00
  • 0538dc77ce For D$, use source 0 through N-1 for MMIO, not 1 through N Andrew Waterman 2017-03-23 13:07:14 -07:00
  • 3951e57789 Force each TLB entry into its own clock-gate group Andrew Waterman 2017-03-22 19:25:02 -07:00
  • 8d7f1d777e Fix an embarrassing typo in the PMPHeterogeneityChecker Andrew Waterman 2017-03-22 17:19:30 -07:00
  • 10c39cb8d6 Disable mprv in D-mode Andrew Waterman 2017-03-22 17:18:04 -07:00
  • d3bda9574c Put page homogeneity checker in PMP Andrew Waterman 2017-03-21 12:01:32 -07:00
  • 9e05200e51 Don't require that PMP ranges be aligned to access size Andrew Waterman 2017-03-20 15:05:42 -07:00
  • 29e67279ba add comments Andrew Waterman 2017-03-20 15:05:15 -07:00
  • 4c8be13a4d Improve homogeneity circuit QoR Andrew Waterman 2017-03-20 13:34:35 -07:00
  • 59d6afa132 mideleg/medeleg not present without less-privileged traps Andrew Waterman 2017-03-20 05:47:35 -07:00
  • 38808f55d5 Share PMP mask gen between I$ and D$ Andrew Waterman 2017-03-20 05:21:50 -07:00
  • 86d84959cf More WIP on PMP Andrew Waterman 2017-03-20 01:34:47 -07:00
  • 2888779422 Flush pipeline from WB stage, not MEM Andrew Waterman 2017-03-20 01:32:10 -07:00
  • 44ca3b60ab Retime PTW response valid bits Andrew Waterman 2017-03-20 01:30:09 -07:00
  • a03556220c Default TLB size = 32 Andrew Waterman 2017-03-20 01:29:26 -07:00
  • 1875407316 Get TLB permission checks off D$ clock gating critical path Andrew Waterman 2017-03-20 01:21:47 -07:00
  • a4164348b4 Expose MXR to S-mode Andrew Waterman 2017-03-20 00:19:38 -07:00
  • 0380aed329 PUM -> SUM Andrew Waterman 2017-03-19 21:38:50 -07:00
  • 2a413e4496 Remove fruitless debug() Andrew Waterman 2017-03-16 15:28:42 -07:00
  • 29414f3a23 Simplify interrupt-stack discipline Andrew Waterman 2017-03-16 12:54:08 -07:00
  • 723352c3e2 Mitigate some more PMP critical paths Andrew Waterman 2017-03-15 18:00:32 -07:00
  • 7484f27ed3 Don't gate exception-cause pipeline registers separately Andrew Waterman 2017-03-15 15:25:55 -07:00
  • 3ea822c2cf Make blocking L1 D$ the default Andrew Waterman 2017-03-15 15:23:30 -07:00
  • 487b8db5ef Address some PMP critical paths Andrew Waterman 2017-03-15 15:22:39 -07:00
  • 03fb334c4c Take mprv calculation off critical path Andrew Waterman 2017-03-15 15:21:13 -07:00
  • f0796f0509 Pass correct access size information to PMP checker Andrew Waterman 2017-03-15 15:18:56 -07:00
  • a6874c03f7 Remove DecoupledTLB Andrew Waterman 2017-03-15 15:17:40 -07:00
  • 78f9f6b9ef When SFENCE.VMA has rs2 != x0, don't flush global mappings Andrew Waterman 2017-03-15 12:50:05 -07:00
  • 1b950128e1 PTW should always use S-mode privilege Andrew Waterman 2017-03-15 12:04:29 -07:00
  • aace526857 WIP on PMP Andrew Waterman 2017-03-15 01:18:39 -07:00
  • b1b405404d Set PRV=M when entering debug mode Andrew Waterman 2017-03-14 14:37:09 -07:00
  • cf168e419b Support SFENCE.VMA rs1 argument Andrew Waterman 2017-03-14 13:54:49 -07:00
  • 797c18b8db Make some requirement failures more verbose (#608) Henry Cook 2017-03-23 21:55:11 -07:00
  • bd08f10816 tilelink2: make sink ids optional (#607) Wesley W. Terpstra 2017-03-23 18:19:04 -07:00
  • 19eb9b6906 l1tol2: put a flow Q on the exits (#606) Wesley W. Terpstra 2017-03-23 16:28:32 -07:00
  • 055b8ba1f0 rocket: avoid LinkedHashMap.keys to preserve traversal order (#603) Henry Cook 2017-03-22 14:38:33 -07:00
  • 4f78eafbdf Merge pull request #602 from ucb-bar/tl-mmio-pipeline Wesley W. Terpstra 2017-03-21 14:59:11 -07:00
  • 76f083b469 FIFOFixer: Not all D-channel messages are A-channel responses Andrew Waterman 2017-03-21 14:15:16 -07:00
  • 3609254e4a There's no structural hazard on MMIO store responses Andrew Waterman 2017-03-21 13:52:06 -07:00
  • 5eae7e1da4 make DCache s1_nack less conservative for pipelined MMIO requests Yunsup Lee 2017-03-21 09:03:50 -07:00
  • 4c00066746 rocket: describe dcache as two clients (fifo+cached) Wesley W. Terpstra 2017-03-20 20:58:07 -07:00
  • 81d717e82f coreplex: guarantee FIFO for those tiles that need it Wesley W. Terpstra 2017-03-20 18:52:03 -07:00
  • 198afddb4b tilelink2: add the FIFOFixer Wesley W. Terpstra 2017-03-20 16:29:03 -07:00
  • c33f31dd3c tilelink2 RAMModel: weaken fifo requirement check Wesley W. Terpstra 2017-03-20 15:42:09 -07:00
  • 930438adba tilelink2 SourceShrinker: destroy FIFO behaviour Wesley W. Terpstra 2017-03-20 15:30:58 -07:00
  • fd521c56a6 tilelink2: add client-side FIFO parameterization Wesley W. Terpstra 2017-03-20 15:15:54 -07:00
  • d4c9c13fb4 Merge pull request #600 from ucb-bar/monitor-spec Wesley W. Terpstra 2017-03-20 15:23:34 -07:00
  • 4eef317e84 RegisterRouter: support devices with gaps Wesley W. Terpstra 2017-03-20 14:48:51 -07:00
  • 431cb41e27 tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E Wesley W. Terpstra 2017-03-20 13:41:29 -07:00
  • 04892fea01 Monitor: support early ack Wesley W. Terpstra 2017-03-20 13:41:19 -07:00
  • 278f6fea24 tilelink2: define is{Request,Response} based on spec Wesley W. Terpstra 2017-03-20 13:27:24 -07:00
  • 778e189bba Monitor: ProbeAckData and ReleaseData may carry an error Wesley W. Terpstra 2017-03-20 11:44:13 -07:00
  • 48c7aed4e1 Monitor: any probe supported by the client is legal Wesley W. Terpstra 2017-03-20 11:34:19 -07:00
  • 5a50acfd9d Merge pull request #595 from ucb-bar/ignore-tl-c Wesley W. Terpstra 2017-03-19 18:49:11 -07:00
  • 0c92283a61 rocket icache: tie off b ready Wesley W. Terpstra 2017-03-19 17:18:50 -07:00
  • c9459fe4eb tilelink2 Xbar: don't use unnecessary ports Wesley W. Terpstra 2017-03-19 17:02:24 -07:00
  • 7971947d6c tilelink2 Monitor: don't inspect bits if valid is forbidden Wesley W. Terpstra 2017-03-19 16:34:23 -07:00
  • a4ca424a22 AHBToTL: finally get the error signal right? (#594) Wesley W. Terpstra 2017-03-18 22:24:20 -07:00
  • d4272db067 travis: only run 4 jobs at once (#593) Wesley W. Terpstra 2017-03-18 04:14:50 -07:00
  • f6daa782d3 AHBToTL: fix the order of updates to d_pause (#592) Wesley W. Terpstra 2017-03-17 19:34:40 -07:00
  • dcc9827ab4 Rename Prci.scala to Clint.scala (#591) Megan Wachs 2017-03-17 15:36:10 -07:00
  • db55a1d755 Fragmenter: fix a bug when underlying device supports larger bursts (#589) Wesley W. Terpstra 2017-03-17 11:00:49 -07:00
  • eb953c40f0 Merge pull request #587 from ucb-bar/ahb-fix Wesley W. Terpstra 2017-03-16 20:55:39 -07:00
  • 9b5b3279a6 AHBToTL: don't report error during idle cycles Wesley W. Terpstra 2017-03-16 18:18:29 -07:00
  • 5efd38bf97 apb: put both aFlow options under regression Wesley W. Terpstra 2017-03-16 15:35:30 -07:00
  • 882a7ff8ff TLToAPB: use the now standard aFlow parameter name Wesley W. Terpstra 2017-03-16 15:34:28 -07:00