Andrew Waterman
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fd727bf8aa
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add some of the zedboard fpga infrastructure
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
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2013-01-06 03:58:10 -08:00 |
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Andrew Waterman
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e12af07722
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update to newest rocket
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2012-11-25 04:40:46 -08:00 |
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Yunsup Lee
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4d73e6e38a
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revamp vector yet again with new D$
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2012-11-18 03:14:22 -08:00 |
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Andrew Waterman
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b58214d7e3
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remove more global constants
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2012-11-17 17:25:43 -08:00 |
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Andrew Waterman
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e2afae011a
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factor out global constants
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2012-11-06 08:18:40 -08:00 |
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Andrew Waterman
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0c372fc9ec
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refactor I$ config into RocketConfiguration
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2012-11-04 17:00:19 -08:00 |
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Henry Cook
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538b23c223
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Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles
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2012-10-23 12:52:59 -07:00 |
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Yunsup Lee
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3edc1f42aa
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revamp the backup memory link in the vlsi backend
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2012-10-23 03:31:34 -07:00 |
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Andrew Waterman
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367b5489d1
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first crack at continuous compilation/testing flow
try it out: cd emulator; make test
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2012-10-19 04:09:07 -07:00 |
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Andrew Waterman
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edf0eeed01
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integrate updated rocket/uncore
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2012-10-18 17:51:41 -07:00 |
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Huy Vo
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24a49350cc
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reference chip design
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2012-10-09 13:05:56 -07:00 |
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