Andrew Waterman fd727bf8aa add some of the zedboard fpga infrastructure ... you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness for VCS simulation yet.		2013-01-06 03:58:10 -08:00
..
.gitignore	reference chip design	2012-10-09 13:05:56 -07:00
fpga.scala	add some of the zedboard fpga infrastructure	2013-01-06 03:58:10 -08:00
RocketChip.scala	update to newest rocket	2012-11-25 04:40:46 -08:00