riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,645 Commits 1 Branch 0 Tags 13 MiB
fc85a3ce02
Commit Graph

4645 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Wesley W. Terpstra
fc3b72084f tilelink2: add a rational clock crossing adapter 2017-01-26 20:07:28 -08:00
Wesley W. Terpstra
4b70386393 AsyncCrossing: disambiguate the file name 2017-01-26 20:07:28 -08:00
Wesley W. Terpstra
5cf4b0632d RationalCrossing: clock crossing between related clock domains 2017-01-26 20:07:28 -08:00
Jack Koenig
1285fa909f Bump chisel and firrtl (#531) 2017-01-26 17:29:26 -08:00
Jim Lawson
3c1dac8c68 Match chisel3 userootunmanageddir - use RootProject/lib as unmanagedBase. (#526) 
This anticipates ucb-bar/chisel3#448. When rocket-chip uses that version of chisel3, the extra copy to chisel3/lib may be removed.
 2017-01-26 11:11:14 -08:00
Henry Cook
0fe2899c74 [tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528) 2017-01-25 12:10:49 -08:00
Wesley W. Terpstra
d1dedd25e7 Merge pull request #529 from ucb-bar/physical-optimization 
Physical optimization
 2017-01-24 18:59:07 -08:00
Wesley W. Terpstra
6ff35a387a tilelink2: disable A=>D bypass in ToAXI4 whenever possible 2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
64e1de751d axi4: add a minLatency parameter 2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
46cdfc2b45 diplomacy: find names of LazyModules also in Seq() member values (#527) 2017-01-24 18:10:37 -08:00
Wesley W. Terpstra
3fc55298ef coreplex: provide coherence managers with geometry information 2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
d4b3a0f0be diplomacy: support given bits in AddressDecoder 2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
c0b6d31377 tilelink2: Delayer adapter useful for unit tests 2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
b3ef146805 Merge pull request #523 from ucb-bar/buffer-move 
coreplex: move TLBuffers for L2 and socBus
 2017-01-21 14:53:51 -08:00
Wesley W. Terpstra
38c9ddffcc BankedL2: move TLFilter BEFORE coherence manager 
This lets smart caches exclude the sets that are filtered.
 2017-01-21 13:23:07 -08:00
Wesley W. Terpstra
dcadd5a006 coreplex: move TLBuffers for L2 and socBus 2017-01-20 22:23:36 -08:00
Wesley W. Terpstra
e8ce32a156 Merge pull request #515 from ucb-bar/cache-cork 
Cache cork
 2017-01-19 20:00:51 -08:00
Wesley W. Terpstra
9dc7f180b6 diplomacy: support zero-port Nodes 2017-01-19 19:08:01 -08:00
Wesley W. Terpstra
c0496fab29 regression: disable build that times out on Travis 2017-01-19 19:07:59 -08:00
Wesley W. Terpstra
5d70265e86 rocket: L1 only needs cache-line transfer sizes 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
3a5e5a65f8 coreplex: support multiple memory channels via diplomatic trickery 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
e7b35b4bb6 diplomacy: support multiple ports behind a BlindNode 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
258abc5629 coreplex: re-enable stateless L2 config 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
4bdb2e5d68 tilelink2 Monitor: ReleaseAck source does not count 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
fbf1073586 tilelink2: CacheCork - terminate caching 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
bf7823f1c8 tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
Henry Cook
e03ba637f4 [regression] remove FancyMemTest (timing out) 2017-01-19 17:48:04 -08:00
Henry Cook
c1b7c84f09 [rocket] bugfix: RoccExampleConfig looks up PAddrBits too early 2017-01-19 17:48:04 -08:00
Henry Cook
e0411c6cde [coreplex] bugfix: re-enable multicore configs via WithNCores 2017-01-19 17:48:04 -08:00
Henry Cook
307f938b88 [rocket] bugfix: fixes #517 2017-01-19 17:48:04 -08:00
Megan Wachs
4fe75965a0 Merge pull request #518 from ucb-bar/dtm_regression 
jtag_dtm: Update regression to run and pass.
 2017-01-18 14:39:53 -08:00
Megan Wachs
e22b01a6fa jtag_dtm: Update regression to run and pass. 2017-01-18 12:08:13 -08:00
Henry Cook
1b31dfa700 Update sbt to 13.12 (#514) 
Closes #496
 2017-01-17 16:26:22 -08:00
Henry Cook
9a6634cd40 Add TLBuffers on the L1 backends and blind exit points (#513) 
* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
 2017-01-17 11:57:23 -08:00
Henry Cook
74b6a8d02b Refactor Tile to use cake pattern (#502) 
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
 2017-01-16 18:24:08 -08:00
Minux Ma
622e311962 Fix emulator argument processing for unknown DTM arguments (#498) 
Revision 7e79421 (issue #484) makes emulator.cc rejecting any unrecognized
+arg "legacy" arguments, however, this breaks riscv-torture emulator tests
as it needs to pass +signature to the DTM.

I think it is actually impossible to check for unknown argument here
unless we hardcode a list of all arguments recognized by fesrv. Fix this
issue by passing all arguments starting with the first unknown argument
to DTM.

Updates #484.

Signed-off-by: Minux Ma <minux.ma@gmail.com>
 2017-01-16 13:42:45 -08:00
GuzTech
8157cf1ede Perform integer division when parsing rocketchip.DefaultConfig.conf (#493) 2017-01-13 16:40:02 -08:00
Wesley W. Terpstra
52bb6cd9d9 Configs: use a uniform syntax without Match exceptions (#507) 
* Configs: use a uniform syntax without Match exceptions

The old style of specifying Configs used total functions.  The only way to
indicate that a key was not matched was to throw an exception.  Not only was
this a performance concern, but it also caused confusing error messages
whenever you had a match failure from a lookup within a lookup.  The
exception could get handled by an outer-lookup that then reported the wrong
key as missing.
 2017-01-13 14:41:19 -08:00
Jacob Chang
b448387899 Merge pull request #508 from ucb-bar/jchang 
Add iterator function to LazyModule to iterate over all nodes
 2017-01-13 10:09:50 -08:00
Jacob Chang
59eb7c24ee Add iterator function to LazyModule to iterate over all nodes 2017-01-12 15:21:10 -08:00
Andrew Waterman
f1cb06142e bump tools 2017-01-11 13:21:55 -08:00
Andrew Waterman
71c4b000b3 Don't special-case power-of-2 replacement policy for BTB 
PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage.  Regardless,
this should be a second-order effect, so using FIFO always is fine.
 2017-01-11 13:21:55 -08:00
Jacob Chang
c531093898 Fix bug introduced with Fuzzer when nOperations is power of 2 (#492) 2016-12-15 19:10:53 -08:00
Wesley W. Terpstra
4471e0de27 Merge pull request #494 from ucb-bar/diplomatic-apb 
Diplomatic apb
 2016-12-15 17:45:20 -08:00
Wesley W. Terpstra
a9b264e582 ahb: lower hsel when idle to save power 2016-12-15 15:32:30 -08:00
Wesley W. Terpstra
16febe7e94 apb: add a TileLink to APB bridge and unittest it 2016-12-15 15:32:27 -08:00
Wesley W. Terpstra
ed091f55e6 apb: diplomatic APB framework 2016-12-15 13:48:50 -08:00
Wesley W. Terpstra
4d87d07343 Merge pull request #491 from ucb-bar/ahb-hready-high 
ahb: don't violate spec with SRAM fuzzing
 2016-12-15 02:50:15 +00:00
Wesley W. Terpstra
a5b8fc2317 RegisterRouterTest: start up with 0 in registers to make VIP testing easier 2016-12-14 15:38:08 -08:00
Wesley W. Terpstra
9d50704b64 ahb: don't violate spec with SRAM fuzzing 2016-12-14 15:18:41 -08:00