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Commit Graph

33 Commits

Author SHA1 Message Date
c85333f826 Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset 2017-09-17 13:51:46 -07:00
215e072e5c test_mode_reset: fix typos 2017-09-17 13:51:40 -07:00
9b75dd7e5b Merge branch 'master' into test_mode_reset 2017-09-15 17:26:11 -07:00
641a8e7eab test_mode_reset: Correct some gender issues. Tie off signals in the test harness 2017-09-15 16:36:35 -07:00
6cda4504ac test_mode_reset: use a cleaner interface with bundles and options instead of individual signals 2017-09-15 12:30:39 -07:00
a0396b63e8 test_mode_reset: fix one bulk-connect gender issue 2017-09-14 13:16:13 -07:00
44edc5fdc3 test_mode_reset: Use simpler apply() method 2017-09-14 13:16:13 -07:00
82c00cb656 reset_catch: Allow Test Mode Overrides 2017-09-14 13:16:13 -07:00
b86f4b9bb7 config: use Field defaults over Config defaults
Also rename some keys that had the same class name as their value's class name.
2017-09-13 11:25:42 -07:00
9c0bfbd500 tile: remove global Field ResetVectorBits
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
2017-09-08 14:50:59 -07:00
ed70b243bd plic: support a configurable number of interrupt register stages 2017-09-07 16:03:34 -07:00
9b55063de6 clint: support a configurable number of interrupt register stages 2017-09-07 16:03:34 -07:00
bf19440db5 SystemBus: use a full buffer on slaves 2017-08-26 02:47:04 -07:00
8783d51c97 jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed 2017-08-14 17:25:47 -07:00
a9b1410f01 BusBlocker: parameterize page granularity 2017-08-08 17:10:01 -07:00
010ba94474 BusBlocker: rename a variable 2017-08-08 17:00:22 -07:00
6d6fc38787 BusBlocker: lock bit should affect the prior PMP address, not next 2017-08-08 17:00:12 -07:00
8f261adc6b BusBlocker: change default policy to deny 2017-08-08 14:19:59 -07:00
0d76e96b88 tilelink: PMP controlled BusBlocker prevents bus accesses 2017-08-08 13:28:01 -07:00
558fc7f293 maskrom: retain data for d channel is not ready 2017-08-07 12:17:10 -07:00
6ef8ee5d4d tilelink: add mask rom 2017-07-31 21:34:04 -07:00
56e28026a6 TLError: does not need to be fast; cut the loop
The SystemBus already has a flow buffer on outputs.
2017-07-29 00:22:21 -07:00
5f81c2243f tilelink: add BusBypass, useful to turn devices off 2017-07-27 20:16:30 -07:00
2e4f1611ed tilelink: Error device supports Acquire
We need this if we want to divert traffic to it from a TL-C slave.
2017-07-27 18:32:58 -07:00
9804bdc34e tilelink: remove obsolete addr_lo signal (#895)
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
2017-07-26 16:01:21 -07:00
01ca3efc2b Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
d09a985729 zero: fix attachment in multichannel case (#870) 2017-07-17 21:48:31 -07:00
35464782b5 PLIC: maxPriorities comes from params 2017-07-13 15:57:10 -07:00
f646bed3ea PLIC: Use longer DTS name for Max Priorities.
I used the singular because there is really only one max priority
2017-07-13 13:37:22 -07:00
0800fd3ed9 PLIC: Add maxPri as well as ndev in DTS 2017-07-13 13:18:50 -07:00
5db0e770d5 tilelink: TestSRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
b2cc4b99ed tilelink: TestSRAM reports errors on illegal access 2017-07-07 21:40:36 -07:00
4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845)
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
2017-07-07 10:48:16 -07:00