Andrew Waterman
66e9f027e0
Add MuxT to mux on Tuple2 and Tuple3
2016-09-07 00:05:38 -07:00
Andrew Waterman
511cc6c5c5
Evaluate arg to Boolean.option lazily
2016-09-07 00:05:38 -07:00
Andrew Waterman
a0dcd42e80
avoid erroneously setting tags valid during flush
2016-09-07 00:05:38 -07:00
Yunsup Lee
fb05f5a07f
remove parameter ExtIOAddrMapEntries ( #250 )
...
with the AddrMap ordering constraint relaxed, this parameter is no longer needed.
2016-09-07 00:05:00 -07:00
Wesley W. Terpstra
d2421654c4
tilelink2: refactor address into addr_hi on ABC and addr_lo on CD
...
We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
2016-09-06 23:46:44 -07:00
Yunsup Lee
b76612f357
relax contraint on adding AddrMapEntry to AddrMap ( #248 )
...
now you can add them in any order. there's an explicit check at the end to figure out whether there are overlapping regions.
2016-09-06 21:53:55 -07:00
Howard Mao
7504498dff
Merge pull request #247 from ucb-bar/replseqmem_pr
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Bump FIRRTL for Sequential Memories
2016-09-06 17:22:18 -07:00
Megan Wachs
e95fe646a3
mem_gen failure doesn't create the target
2016-09-06 16:29:29 -07:00
Howard Mao
bbef3a8d3e
Merge pull request #246 from ucb-bar/fix-configstring-printout-problem
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fix configstring printout with no memory
2016-09-06 15:31:39 -07:00
Megan Wachs
48098f5e2d
Bump FIRRTL to instantiate Sequential Memory Macros
2016-09-06 14:48:28 -07:00
Megan Wachs
1fec9807f6
allow override of vlsi_mem_gen script
2016-09-06 14:44:12 -07:00
Wesley W. Terpstra
aae4230627
tilelink2: fix bugs found by Megan in Legacy converter
2016-09-06 13:12:33 -07:00
Yunsup Lee
56d81b0034
fix configstring printout with no memory
2016-09-06 10:40:11 -07:00
Wesley W. Terpstra
54ab14cd9d
tilelink2: statically optimize numBeats for simple managers
2016-09-05 22:11:03 -07:00
Wesley W. Terpstra
314d6ebd6f
tilelink2: stricter TransferSizes requirements
2016-09-05 22:10:28 -07:00
Wesley W. Terpstra
56170c605c
tilelink2: be more forgiving in what Legacy TL requires
2016-09-05 21:12:51 -07:00
Wesley W. Terpstra
3167539331
tilelink2: Narrower must be little-endian
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
ded246fb95
tilelink2: relax max transfer size; the real requirement is not exceeding alignment
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
cf0291061d
tilelink2: fix a bug in UIntToOH1 triggered if the size was too big
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
9f45212c95
tilelink2: Fragmenter needs to update subaddress
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
757d46279e
tilelink2: expand data correctly in D channel narrower
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
0faa8c4051
tilelink2: fix Xbar bug where Mux1H broke FSM if only one manager
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
a0c25880c7
tilelink2: Monitor should check mask of reconstructed request
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
df32cc3887
tilelink2: be careful; apply Andrew's masking trick everywhere
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
fb262558ee
tilelink2: helper objects should pass source line from where they were invoked
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
1a081b4dd5
tilelink2: Monitor should report which TL connection was the problem
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
cb54df0a8a
tilelink2: tie off unused channels
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
68e64a9859
tilelink2: clarify ready-valid use of RegisterRouter
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
e3b3543841
tilelink2: ensure RegFields don't exceed their bounds
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
8343070639
tilelink2: detect 1-bit overflow in register definitions
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
a1fc01fd6d
tilelink2: prevent mapping the same register twice
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
81162a2dc9
tilelink2: support attaching a DecoupledIO directly to a register
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
6a378e79e3
tilelink2: allow 0-stage backpressure in combinational regmap
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
4746cf00ce
tilelink2: move files to new uncore directory
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
e034775bfa
tilelink2: use the fancy new hasData functions
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
11b0272d91
tilelink2: create optimized hasData method on edges (statically evaluates if known)
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
5db7ae262b
tilelink2: first version of Narrower (only supports uncached IO)
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
b004d54d71
tilelink2: add a Fragmenter adapter
...
God that was a pain in the ass!
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
ecc3c2a4b2
tilelink2: more efficient one-hot circuits
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
3d84795641
tilelink2: use LazyModule(new ...) just like Chisel Module(new ...)
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
2069ca5d8d
tilelink2: pass sourceInfo using implicits in Monitor
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
935b53f3bf
tilelink2: explicitly check that fixed fields never change in multibeat
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
e652cd155b
tilelink2: edge parameters on the same link had better match
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
c411a3e77f
tilelink2: simpler sizes requirement for users to understand
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
ab998c08f1
tilelink2: save some hardware in HintHandler if no BCE
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
18e7d4cd65
tilelink2: make it possible to write Node-only adapters
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
4a401fc480
tilelink2: add a Buffer adapter to insert pipeline stages
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
50f0dee69e
tilelink2: add an IdentityNode for adapters that change nothing
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
9cd2991fb3
tilelink2: AddressSet always has an assigned base address
...
The consensus seems to be that TileLink should not be assigning
addresses dynamically. The reasons:
1. We can come up with another scheme for assigning addresses that is
independent of TileLink. This decoupling is good, because it would
allow us to use the same mechanism for different buses in the SoC.
2. The informational flow of addresses is more likely to naturally follow
the module hierarchy than the TileLike bus topology. Thus, it seems
better to pass address parameterization using Module constructors.
3. Addresses are still checked by TileLink, so using a Module-centric
flow for addresses will not pose a correctness concern.
4. An address need only be provided to a slave on its construction and
TileLink parameterization spreads this globally. Thus, the burden to
manually assign an address is low.
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
ae2bc4da21
tilelink2: refactor RegField into interface and implementation
2016-09-05 20:58:39 -07:00
