Andrew Waterman
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2f8fcebea0
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remove datapath register resets resets
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2012-01-01 16:09:40 -08:00 |
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Andrew Waterman
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a87ad06780
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Automatically infer rocketCAM address width
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2011-12-06 02:05:40 -08:00 |
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Rimas Avizienis
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9d3471a569
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more cache fixes, more test harness debug output
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2011-11-13 23:32:18 -08:00 |
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Rimas Avizienis
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67c7e7e28f
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cache/tlb bugfixes, increased memory size to 256meg
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2011-11-13 13:06:35 -08:00 |
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Rimas Avizienis
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fbd44ea936
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added checks for addresses > physical memory size, increased memsize to 64M
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2011-11-12 23:39:43 -08:00 |
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Rimas Avizienis
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91c252ad08
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fixing output enable signals for data/tag SRAMs
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2011-11-12 15:47:47 -08:00 |
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Rimas Avizienis
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73416f224b
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more tlb/ptw debugging
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2011-11-12 00:25:06 -08:00 |
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Rimas Avizienis
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44926866b7
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updated itlb
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2011-11-11 18:48:34 -08:00 |
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Rimas Avizienis
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e4fa94aa27
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checkpoint
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2011-11-10 17:41:22 -08:00 |
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Rimas Avizienis
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f86d5b1334
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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4bd0263a4a
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added misaligned instruction check, cleaned up badvaddr handling
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2011-11-10 03:38:59 -08:00 |
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Rimas Avizienis
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62407b4668
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more tlb/ptw fixes
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2011-11-10 00:23:29 -08:00 |
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Rimas Avizienis
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c29d2821b4
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cleanup, fixes, initial commit for dtlb.scala
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2011-11-09 21:54:11 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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