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Author	SHA1	Message	Date
Scott Beamer	a59ba39310	bump submodule for fpga-zynq	2015-05-21 11:26:57 -07:00
Scott Beamer	2a5dd907f5	bump chisel version	2015-01-06 16:59:10 -08:00
Scott BeamerandYunsup Lee	5f55ded723	bump fpga submodule	2014-10-06 13:45:12 -07:00
Scott BeamerandYunsup Lee	06bc6a45db	move fpga repo to git@ from https	2014-10-06 13:45:09 -07:00
Scott BeamerandYunsup Lee	f2ca887de3	better fpga configs	2014-09-25 06:47:03 -07:00
Scott BeamerandYunsup Lee	1a101f8de5	don't use latches on mem ports for fpga	2014-09-25 06:46:21 -07:00
Scott BeamerandYunsup Lee	f4e6cd75ab	turn off fpu for default fpga config. ... a larger fpga can use defaultconfig	2014-09-25 06:46:16 -07:00
Scott Beamer	6c6f5a3843	add verilog target to build without simulator	2014-09-03 17:28:45 -07:00
Scott Beamer	13b6ec4712	including better sbt fixes	2014-09-02 15:16:31 -07:00
Scott Beamer	26649b30ed	fixes sbt error during first run	2014-09-02 14:34:55 -07:00
Scott Beamer	83380053de	use fpga backend for fpga	2014-08-26 15:56:27 -07:00
Scott Beamer	63b62394d9	added l2 to fpga ... with new chisel & uncore, it goes into brams	2014-08-20 15:41:07 -07:00
Scott Beamer	d3a8a224fe	README updated for new fpga flow	2014-08-07 14:52:56 -07:00
Scott Beamer	e390eba8ce	convert README to markdown	2014-08-07 14:50:31 -07:00
Scott Beamer	4109d7cc87	newest version of chisel needed for brams	2014-08-07 13:49:31 -07:00
Scott Beamer	cda46b3ce1	use --recursive to populate all submodules. with current instructions you can't run tests because riscv-tests/env isn't pulled in	2014-02-06 16:20:48 -08:00