Wesley W. Terpstra
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452bb2fc80
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dcache fix TinyConfig
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2016-11-18 19:50:34 -08:00 |
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Wesley W. Terpstra
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d1328a6b6f
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rocketchip: remove most uses of GlobalAddrMap
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2016-11-18 19:38:02 -08:00 |
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Henry Cook
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2976fd84e4
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[rocket] resolve cde/config conflicts
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2016-11-18 19:11:34 -08:00 |
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Henry Cook
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8b908465e0
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[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
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2016-11-18 19:04:06 -08:00 |
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Henry Cook
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5f1cc19d71
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[tl2] fix comment explaining permissions
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2016-11-18 19:02:17 -08:00 |
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Henry Cook
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10112da4e7
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[tl2] won't need putthrough opcode
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2016-11-18 19:02:17 -08:00 |
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Wesley W. Terpstra
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001d9821bd
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Merge remote-tracking branch 'origin/master' into tl2-tile
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2016-11-18 18:19:41 -08:00 |
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Wesley W. Terpstra
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5b594ced29
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Plic: support 0 interrupts gracefully
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2016-11-18 18:07:44 -08:00 |
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Wesley W. Terpstra
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13ec3853ed
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junctions: get unit tests running again
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2016-11-18 17:38:46 -08:00 |
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Wesley W. Terpstra
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10dd6070ad
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groundtest: gracefully handle zero uncached ports
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2016-11-18 17:26:28 -08:00 |
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Wesley W. Terpstra
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03bca77b33
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tilelink2 Metadata: cannot assert data good when !valid
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2016-11-18 17:16:12 -08:00 |
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Wesley W. Terpstra
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be8121eeaf
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coreplex: fix clock crossing
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2016-11-18 17:15:57 -08:00 |
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Wesley W. Terpstra
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0082d713af
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coreplex: disable Stateless config until we implement adapter
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2016-11-18 16:23:16 -08:00 |
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Wesley W. Terpstra
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8059d33217
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groundtest: simplify FancyMemtestConfig for now
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2016-11-18 16:18:33 -08:00 |
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Wesley W. Terpstra
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04b9a68ea6
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MergedPutRegression: wait for all Puts if tlMaxClientXacts != 3
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2016-11-18 16:18:33 -08:00 |
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Wesley W. Terpstra
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cd19bf65b8
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regression: fix bad regression that deadlocks SoC with illegal D stall
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2016-11-18 16:18:33 -08:00 |
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Wesley W. Terpstra
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5f7fa3dae5
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regression: remove illegal test which reuses the same ID
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2016-11-18 16:18:33 -08:00 |
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Wesley W. Terpstra
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a6188efc41
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rocketchip: break infinite Config loops
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2016-11-18 16:18:33 -08:00 |
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Wesley W. Terpstra
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37a3c22639
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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Wesley W. Terpstra
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40daea2e15
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util: Config scheme supporting up with ++
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2016-11-18 16:18:30 -08:00 |
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Wesley W. Terpstra
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e5febcfa33
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rocketchip: there are no more useful parameters to dump
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2016-11-18 14:31:42 -08:00 |
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Wesley W. Terpstra
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30425d1665
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rocketchip: eliminate all Knobs
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2016-11-18 14:31:42 -08:00 |
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Wesley W. Terpstra
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119ccae9af
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rocketchip: don't use explicit cde namespace
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2016-11-18 14:31:42 -08:00 |
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Richard Xia
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87cbd5c893
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Merge pull request #439 from ucb-bar/add-chip-configs
Add various granular configs.
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2016-11-18 12:12:50 -08:00 |
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Richard Xia
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bab504cc3f
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Add various granular and composable configs.
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2016-11-18 11:30:07 -08:00 |
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Henry Cook
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5bd343bac8
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[rocket] d_last && d.fire() => d_done
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2016-11-17 18:42:59 -08:00 |
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Henry Cook
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1ddccb1b33
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[rocket] add TODO for single cycle ack
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2016-11-17 18:42:59 -08:00 |
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Henry Cook
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94086f2270
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[tl2] broadcast hub probe port width bugfix
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2016-11-17 18:42:59 -08:00 |
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Henry Cook
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960c2723ab
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[tl2] MemoryOpCategories: use def to supply Cat'd consts
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2016-11-17 18:42:59 -08:00 |
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Wesley W. Terpstra
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179c93db42
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tilelink2 broadcast: make it controlled via Config
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2016-11-17 17:26:49 -08:00 |
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Wesley W. Terpstra
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f4ca5ea1f3
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rocketchip: match simulated memory width to ExtMem.beatBytes
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2016-11-17 15:40:47 -08:00 |
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Wesley W. Terpstra
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12d0d8bea2
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rocketchip: remove obsolete bus configuration
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2016-11-17 14:30:15 -08:00 |
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Wesley W. Terpstra
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c82b371354
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rocketchip: remove obsolete TL1 config
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2016-11-17 14:24:45 -08:00 |
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Wesley W. Terpstra
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dfc3a0dafb
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tilelink2: do not depend on obsolete TL1 configuration
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2016-11-17 14:07:53 -08:00 |
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Wesley W. Terpstra
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8a0ecdaaad
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groundtest: ComparatorConfig lives again
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2016-11-17 11:07:49 -08:00 |
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Henry Cook
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92e233d596
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[groundtest] testramaddr constant in package
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2016-11-16 18:42:56 -08:00 |
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Henry Cook
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e1992d7c55
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[rocket] grant addr bugfix
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2016-11-16 18:12:06 -08:00 |
|
Henry Cook
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84f249bd03
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[rocketchip] BigInt cast
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2016-11-16 18:11:06 -08:00 |
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Henry Cook
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da7ecfd189
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[rocket] probeack vs probeackdata bugfix
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2016-11-16 17:27:02 -08:00 |
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Henry Cook
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75d4347192
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[groundtest] runs tests with new coreplex and top
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2016-11-16 17:05:53 -08:00 |
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Henry Cook
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24e3216fcf
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coreplex: allow zero interrupt sink/sources
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2016-11-16 16:50:36 -08:00 |
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Henry Cook
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479bc82f03
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tilelink2 Broadcast: improve bufferless throughput
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2016-11-16 16:50:36 -08:00 |
|
Henry Cook
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408e78e35e
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rocketchip Periphery: ExtMem and ExtBus Configs
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2016-11-16 16:50:30 -08:00 |
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Henry Cook
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1f51564577
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[rocket] dcache probe ack data bugfix
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2016-11-16 14:25:21 -08:00 |
|
Henry Cook
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66a2c5544e
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[rocket] L1D acquire addr bugfix
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2016-11-16 13:38:52 -08:00 |
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Henry Cook
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c5e03c9c76
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[rocket] dcache release addr bugfix
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2016-11-16 13:14:51 -08:00 |
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Richard Xia
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81d98304dc
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Merge pull request #438 from ucb-bar/bump-riscv-tools-for-riscv-test-updates
Bump riscv-tools to bump riscv-tests to pull in OpenOCD port randomization feature.
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2016-11-16 12:26:48 -08:00 |
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Wesley W. Terpstra
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06a7b95d0d
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tilelink2 broadcast: support bufferless Config
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2016-11-16 12:25:11 -08:00 |
|
Wesley W. Terpstra
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3703ed39f7
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groundtest: PTW needs atomics
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2016-11-16 12:16:54 -08:00 |
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Wesley W. Terpstra
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5d2e637a4a
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tilelink2 Legacy: uncached TL never needs manager_xact_id
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2016-11-16 12:16:25 -08:00 |
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