Andrew Waterman
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ce202c73d1
|
add fsgnj[n|x].[s|d]
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2012-02-14 04:24:35 -08:00 |
|
Andrew Waterman
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1d604bcd49
|
remove top-level Makefile
new, simpler build instructions are in the README.
note that for "make run-asm-tests-debug" you need to update your fesvr.
|
2012-02-14 02:53:43 -08:00 |
|
Andrew Waterman
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15dc2d8c40
|
add fp writeback arbitration logic
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2012-02-14 00:32:25 -08:00 |
|
Henry Cook
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0671a99712
|
NBcache works with associativities other than powers of 2
|
2012-02-13 21:44:32 -08:00 |
|
Henry Cook
|
6d36168183
|
Fixed two associative nbcache bugs, one in amo replays and one in the flush unit
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2012-02-13 21:44:32 -08:00 |
|
Andrew Waterman
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0366465cb1
|
parameterize the scoreboards
|
2012-02-13 18:12:23 -08:00 |
|
Andrew Waterman
|
6c2d8a37ae
|
remove a partial update that makes chisel barf
chisel regards it as a combinational loop, even though it isn't.
|
2012-02-13 16:45:29 -08:00 |
|
Andrew Waterman
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c78c738f60
|
minor cleanups
|
2012-02-13 03:13:49 -08:00 |
|
Andrew Waterman
|
b5a19a54a3
|
add fcvt.[s|d].[w|l][u]
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2012-02-13 02:01:26 -08:00 |
|
Andrew Waterman
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a4a9d2312c
|
add fcvt.[w|l][u].[s|d], f[eq|lt|le].[s|d]
|
2012-02-13 01:30:01 -08:00 |
|
Andrew Waterman
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069037ff3a
|
add FP recoding
|
2012-02-12 23:31:50 -08:00 |
|
Andrew Waterman
|
25ecfb9bbc
|
clean up caches
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
|
2012-02-12 20:32:06 -08:00 |
|
Andrew Waterman
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08b6517a23
|
add FP ops mftx, mxtf, mtfsr, mffsr
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2012-02-12 20:12:53 -08:00 |
|
Andrew Waterman
|
9bb1558a34
|
WIP on FPU
|
2012-02-12 04:36:01 -08:00 |
|
Andrew Waterman
|
50a283d311
|
move store data generation into EX stage
doing so removes it from the critical path of FP store unrecoding.
|
2012-02-12 01:35:55 -08:00 |
|
Andrew Waterman
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725190d0ee
|
update to new chisel
|
2012-02-11 17:20:33 -08:00 |
|
Andrew Waterman
|
f8b937d590
|
fix 32-bit divider bug
thanks, torture!
also, tidied up the code a bit.
|
2012-02-09 03:47:59 -08:00 |
|
Andrew Waterman
|
03ee49f424
|
fix 32-bit AMOs to upper halves of 64-bit words
thanks, torture!
|
2012-02-09 03:31:47 -08:00 |
|
Yunsup Lee
|
f47d888feb
|
vvcfgivl and vsetvl works
|
2012-02-09 02:35:21 -08:00 |
|
Andrew Waterman
|
92493ad153
|
fix mul/div kill bug
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
|
2012-02-09 02:26:03 -08:00 |
|
Andrew Waterman
|
128ec567ed
|
make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
|
2012-02-09 01:34:00 -08:00 |
|
Yunsup Lee
|
fcc8081c4d
|
hook up the vector command queue
|
2012-02-09 01:28:16 -08:00 |
|
Andrew Waterman
|
8b6b0f5367
|
add external memory request interface for vec unit
|
2012-02-08 22:30:45 -08:00 |
|
Yunsup Lee
|
9285a52f25
|
initial vu integration
|
2012-02-08 21:43:45 -08:00 |
|
Andrew Waterman
|
10b5a0006c
|
fix mul/div to rd=0
|
2012-02-08 20:11:57 -08:00 |
|
Andrew Waterman
|
a1855b12c2
|
clean up queues
|
2012-02-08 17:55:05 -08:00 |
|
Andrew Waterman
|
990e3a1b34
|
fix fpu port direction bug
|
2012-02-08 15:19:26 -08:00 |
|
Andrew Waterman
|
71c8d3fd41
|
reorganize directory structure
|
2012-02-08 15:13:08 -08:00 |
|
Andrew Waterman
|
b3f6f9a5fd
|
fix BTB misprediction check for negative addresses
also index BTB with PC, not PC+4
|
2012-02-08 15:05:28 -08:00 |
|
Andrew Waterman
|
e9da2cf66a
|
improve id/ex datapath
move operand selection into decode stage; simplify bypassing
|
2012-02-08 06:47:26 -08:00 |
|
Andrew Waterman
|
d471a8b2da
|
arbitrate for LLFU writebacks in MEM stage
|
2012-02-08 04:21:05 -08:00 |
|
Andrew Waterman
|
ebed56500e
|
fix mul/wb hazard checks
I erroneously assumed that those instructions set id_wen.
|
2012-02-08 01:56:11 -08:00 |
|
Andrew Waterman
|
5403d069e9
|
add fp loads/stores
|
2012-02-07 23:54:25 -08:00 |
|
Christopher Celio
|
1be9d15944
|
Fixed bug regarding case sensitivity regarding ioICache,ioDCache
|
2012-02-07 14:07:42 -08:00 |
|
Andrew Waterman
|
fde8e3b696
|
clean up bypassing/hazard checking a bit
|
2012-02-06 17:26:45 -08:00 |
|
Henry Cook
|
41c4e10c37
|
Workaround for another frakking extraction error in the C backend. C and VLSI backends now both boot kernel with associativity on
|
2012-02-02 21:53:57 -08:00 |
|
Andrew Waterman
|
99a959e6b1
|
remove pc+4 piperegs and add new ex pc+4 adder
|
2012-02-02 13:33:27 -08:00 |
|
Andrew Waterman
|
01a156eb98
|
make # of dcache lines configurable
|
2012-02-01 21:11:45 -08:00 |
|
Andrew Waterman
|
b1bbf56b74
|
clean up wb->id bypass
|
2012-02-01 16:41:18 -08:00 |
|
Henry Cook
|
c5a4eaa0a1
|
Associative cache, boots kernel
|
2012-02-01 13:26:04 -08:00 |
|
Henry Cook
|
281abfbccb
|
New Mux1H constructor
|
2012-02-01 13:24:28 -08:00 |
|
Andrew Waterman
|
38c9105ea1
|
fix mul/div deadlock bug
If independent multiplies or independent divides were issued
back-to-back, the second wouldn't execute, causing the register
to be busy forever.
|
2012-01-30 21:14:28 -08:00 |
|
Andrew Waterman
|
bd241ea237
|
fix when badvaddr is set
|
2012-01-30 17:15:42 -08:00 |
|
Andrew Waterman
|
a96c92f58d
|
enable amomin[u]/amomax[u
|
2012-01-26 20:45:04 -08:00 |
|
Andrew Waterman
|
a7999d4525
|
don't flush I$ unless fence.i commits
otherwise, we might not make forward progress.
|
2012-01-26 20:37:09 -08:00 |
|
Andrew Waterman
|
32f5f420f3
|
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
|
2012-01-26 20:12:42 -08:00 |
|
Andrew Waterman
|
41855a6d47
|
fix missing "otherwise" in PCR file
this fixes timer interrupts for VLSI backend.
|
2012-01-26 19:33:55 -08:00 |
|
Andrew Waterman
|
7172ddd050
|
don't flush pipeline after MFPCR
|
2012-01-24 18:40:08 -08:00 |
|
Andrew Waterman
|
97c379f1d7
|
made I$ associative
|
2012-01-24 16:51:30 -08:00 |
|
Henry Cook
|
aa3465699b
|
LFSR now a util
|
2012-01-24 15:26:19 -08:00 |
|