Wesley W. Terpstra
|
d9a203b0f0
|
PositionalMultiQueue: convert 'next' to a single write port
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2016-11-22 18:38:55 -08:00 |
|
Wesley W. Terpstra
|
13190a5de0
|
rocketchip: re-add AXI4 interface
|
2016-11-22 17:27:58 -08:00 |
|
Wesley W. Terpstra
|
c230580157
|
coreplex: rename RocketPlex => RocketTiles
|
2016-11-22 17:27:58 -08:00 |
|
Wesley W. Terpstra
|
bbabcf67ff
|
coreplex: width adapter should happen as part of coherence manager
In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
|
2016-11-22 17:27:58 -08:00 |
|
Wesley W. Terpstra
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a140b07009
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rocketchip: cut coreplex from rocketchip
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2016-11-22 17:27:58 -08:00 |
|
Wesley W. Terpstra
|
c80ee06472
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rocketchip: configString is a lazy property of outer
|
2016-11-22 17:27:58 -08:00 |
|
Andrew Waterman
|
5f3fb64ef0
|
Per ABI, only x1 and x5 should be treated as function returns
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
|
2016-11-22 12:01:05 -08:00 |
|
Wesley W. Terpstra
|
3d644b943c
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coreplex: configString is a property of the RISCVPlatform
|
2016-11-21 21:13:26 -08:00 |
|
Wesley W. Terpstra
|
e8be365b5d
|
rocketchip: remove GlobalAddrMap completely
|
2016-11-21 21:13:26 -08:00 |
|
Wesley W. Terpstra
|
5fe107bb07
|
rocket: pass scratchpad address to block dcache
|
2016-11-21 21:13:26 -08:00 |
|
Wesley W. Terpstra
|
c18bc07bbc
|
TLB: determine RWX from TL2 properties directly
|
2016-11-21 21:13:26 -08:00 |
|
Henry Cook
|
28c6be90ab
|
[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
|
2016-11-20 19:36:51 -08:00 |
|
Henry Cook
|
ff9b5bf8fc
|
[rocket] nbdcache release bugfix
|
2016-11-20 19:07:06 -08:00 |
|
Henry Cook
|
3f47d5b5eb
|
[rocket] re-enable working NBDcache (passes Tracegen)
|
2016-11-19 19:19:16 -08:00 |
|
Henry Cook
|
c31b41a7ac
|
[tl2] add grant finisher comment
|
2016-11-19 19:16:43 -08:00 |
|
Colin Schmidt
|
9dd12545d0
|
[Rocket] Send correct type for iomshr reqs
Also contain grow param bugfix
|
2016-11-19 19:04:06 -08:00 |
|
Wesley W. Terpstra
|
32a1c27441
|
rocket: disable nbdcache until it's fully ported
|
2016-11-18 19:55:24 -08:00 |
|
Wesley W. Terpstra
|
452bb2fc80
|
dcache fix TinyConfig
|
2016-11-18 19:50:34 -08:00 |
|
Wesley W. Terpstra
|
d1328a6b6f
|
rocketchip: remove most uses of GlobalAddrMap
|
2016-11-18 19:38:02 -08:00 |
|
Henry Cook
|
2976fd84e4
|
[rocket] resolve cde/config conflicts
|
2016-11-18 19:11:34 -08:00 |
|
Henry Cook
|
8b908465e0
|
[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
|
2016-11-18 19:04:06 -08:00 |
|
Henry Cook
|
5f1cc19d71
|
[tl2] fix comment explaining permissions
|
2016-11-18 19:02:17 -08:00 |
|
Henry Cook
|
10112da4e7
|
[tl2] won't need putthrough opcode
|
2016-11-18 19:02:17 -08:00 |
|
Wesley W. Terpstra
|
001d9821bd
|
Merge remote-tracking branch 'origin/master' into tl2-tile
|
2016-11-18 18:19:41 -08:00 |
|
Wesley W. Terpstra
|
5b594ced29
|
Plic: support 0 interrupts gracefully
|
2016-11-18 18:07:44 -08:00 |
|
Wesley W. Terpstra
|
13ec3853ed
|
junctions: get unit tests running again
|
2016-11-18 17:38:46 -08:00 |
|
Wesley W. Terpstra
|
10dd6070ad
|
groundtest: gracefully handle zero uncached ports
|
2016-11-18 17:26:28 -08:00 |
|
Wesley W. Terpstra
|
03bca77b33
|
tilelink2 Metadata: cannot assert data good when !valid
|
2016-11-18 17:16:12 -08:00 |
|
Wesley W. Terpstra
|
be8121eeaf
|
coreplex: fix clock crossing
|
2016-11-18 17:15:57 -08:00 |
|
Wesley W. Terpstra
|
0082d713af
|
coreplex: disable Stateless config until we implement adapter
|
2016-11-18 16:23:16 -08:00 |
|
Wesley W. Terpstra
|
8059d33217
|
groundtest: simplify FancyMemtestConfig for now
|
2016-11-18 16:18:33 -08:00 |
|
Wesley W. Terpstra
|
04b9a68ea6
|
MergedPutRegression: wait for all Puts if tlMaxClientXacts != 3
|
2016-11-18 16:18:33 -08:00 |
|
Wesley W. Terpstra
|
cd19bf65b8
|
regression: fix bad regression that deadlocks SoC with illegal D stall
|
2016-11-18 16:18:33 -08:00 |
|
Wesley W. Terpstra
|
5f7fa3dae5
|
regression: remove illegal test which reuses the same ID
|
2016-11-18 16:18:33 -08:00 |
|
Wesley W. Terpstra
|
a6188efc41
|
rocketchip: break infinite Config loops
|
2016-11-18 16:18:33 -08:00 |
|
Wesley W. Terpstra
|
37a3c22639
|
rocketchip: move from using cde to config
|
2016-11-18 16:18:33 -08:00 |
|
Wesley W. Terpstra
|
40daea2e15
|
util: Config scheme supporting up with ++
|
2016-11-18 16:18:30 -08:00 |
|
Wesley W. Terpstra
|
e5febcfa33
|
rocketchip: there are no more useful parameters to dump
|
2016-11-18 14:31:42 -08:00 |
|
Wesley W. Terpstra
|
30425d1665
|
rocketchip: eliminate all Knobs
|
2016-11-18 14:31:42 -08:00 |
|
Wesley W. Terpstra
|
119ccae9af
|
rocketchip: don't use explicit cde namespace
|
2016-11-18 14:31:42 -08:00 |
|
Richard Xia
|
bab504cc3f
|
Add various granular and composable configs.
|
2016-11-18 11:30:07 -08:00 |
|
Henry Cook
|
5bd343bac8
|
[rocket] d_last && d.fire() => d_done
|
2016-11-17 18:42:59 -08:00 |
|
Henry Cook
|
1ddccb1b33
|
[rocket] add TODO for single cycle ack
|
2016-11-17 18:42:59 -08:00 |
|
Henry Cook
|
94086f2270
|
[tl2] broadcast hub probe port width bugfix
|
2016-11-17 18:42:59 -08:00 |
|
Henry Cook
|
960c2723ab
|
[tl2] MemoryOpCategories: use def to supply Cat'd consts
|
2016-11-17 18:42:59 -08:00 |
|
Wesley W. Terpstra
|
179c93db42
|
tilelink2 broadcast: make it controlled via Config
|
2016-11-17 17:26:49 -08:00 |
|
Wesley W. Terpstra
|
f4ca5ea1f3
|
rocketchip: match simulated memory width to ExtMem.beatBytes
|
2016-11-17 15:40:47 -08:00 |
|
Wesley W. Terpstra
|
12d0d8bea2
|
rocketchip: remove obsolete bus configuration
|
2016-11-17 14:30:15 -08:00 |
|
Wesley W. Terpstra
|
c82b371354
|
rocketchip: remove obsolete TL1 config
|
2016-11-17 14:24:45 -08:00 |
|
Wesley W. Terpstra
|
dfc3a0dafb
|
tilelink2: do not depend on obsolete TL1 configuration
|
2016-11-17 14:07:53 -08:00 |
|