Yunsup Lee
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0d245741bc
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add multichannel NASTI support in Verilog testbench
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2015-11-05 10:48:32 -08:00 |
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Howard Mao
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9dabcab9c2
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Get rid of MemIO in Top and replace with AXI throughout
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2015-11-05 10:48:32 -08:00 |
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Yunsup Lee
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a175afae73
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make ZscaleChip work with new parameters framework
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2015-10-25 10:24:39 -07:00 |
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Howard Mao
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4346111d2a
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fix remaining vsim harness typo
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2015-10-19 20:20:14 -07:00 |
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Yunsup Lee
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e7802825c3
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add Zscale testing
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2015-07-17 12:02:02 -07:00 |
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Henry Cook
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d3ccec1044
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Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
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2015-07-02 14:43:30 -07:00 |
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Yunsup Lee
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1cfd9f5a0e
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add LICENSE
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2014-09-12 10:15:04 -07:00 |
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Yunsup Lee
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02c08a156f
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generate consts.vh from chisel source
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2014-09-10 17:14:55 -07:00 |
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Yunsup Lee
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ddfd3ce968
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further generalize fpga/vlsi builds
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2014-09-08 00:21:57 -07:00 |
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Yunsup Lee
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c03c09ec31
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update for rocket-chip release
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2014-08-31 20:26:55 -07:00 |
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