Wesley W. Terpstra
a9a3f7dd4e
tilelink2 RAMModel: include name of test in output
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
345eefd81b
axi4: include unit tests
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a6c6d99848
axi4: prototype Fragmenter
2016-10-12 17:08:49 -07:00
Wesley W. Terpstra
c918aa6d89
axi4: name AdapterNode parameters properly
2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
a423f97844
axi4: parameterized AXI master constraint for aligned access
2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
673cf1fdb5
tilelink2 ToAXI4: must create irrevocable D for now
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
8e92ac32b7
tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
38b6c1c820
tilelink2 axi4: RegisterRouter can cut ready dependency
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
dc26736f32
axi4 tilelink2: include minAlignment and maxAddress in slaves
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
538437384a
tilelink2 Fragmenter: combine AccessAck errors
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
4caa543ad7
tilelink2: Fragmenter should not cut Acquire parameters
...
The correct response to misuse is to fail a requirement check.
Pretending that things are not caches could lead to inconsistency.
2016-10-11 22:38:03 -07:00
Wesley W. Terpstra
6336f94fa2
tilelink2: only caches can support B requests
2016-10-11 22:38:02 -07:00
Wesley W. Terpstra
4a975ca380
tilelink2: add a rightOR to go with our leftOR
2016-10-11 22:38:02 -07:00
Wesley W. Terpstra
b2a5d18e37
diplomacy: simplify address range fragmentation
2016-10-11 22:36:21 -07:00
Wesley W. Terpstra
b0e33f4a39
tilelink2: use TLArbiter in HintHandler
2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
683a2e6785
tilelink2: refactor firstlast helper method
2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
a404cd2abf
tilelink2: use NodeHandle to restore Crossing.node API
2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
876609eb0e
diplomacy: add NodeHandles to support abstraction
2016-10-10 13:15:25 -07:00
Wesley W. Terpstra
97af07eb3e
tilelink2: clarify use of Isolation
2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
76388117bb
regmapper: detect improper reset sequencing in RegisterCrossing
2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
b5f5ef69c1
regmapper: eliminate race condition in RegisterCrossing bypass
2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
f250426728
tilelink2: blow up if the channels carry data when they should not
2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
1b09f1360d
AsyncQueue: adjust register names to match vals
2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
e7f8a7e9ea
AsyncQueue: make it clear that the SyncChain is not Gray specific
2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
52b8121e68
Apply "async_queue: Give names to all the registers which show up in the queue ( #390 )"
...
Adjusted to include names for the new registers.
Changes to RegisterCrossing were discarded.
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
ffb734ac0e
AsyncQueue: disambiguiate the reset_n signal names
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
5ee53c61d6
util: clarify an AsyncQueue corner-case
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
609fd97a71
util: AsyncQueue detect power-down/reset of non-empty queue
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
75bb94017b
util: resynchronize AsyncQueue counters when far side resets
...
If the other clock domain is much faster than ours, it's reset
might be shorter than a single cycle in our domain. In that case,
we need to catch the reset and extend it.
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
5e2609bdd2
AsyncQueueSource: don't feed reset into normal logic!
...
There is no need to block writes to mem during reset.
The Queue must be empty anyway.
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
2f6985efd3
crossings: use flip not flip()
...
This seems to be the more common API
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
6d6aa3eb13
tilelink2: Isolation must also connect reset_n
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
cb7b16f1a9
util: exchange resets between AsyncQueue source and sink
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
8c7d469a95
Revert "async_queue: Give names to all the registers which show up in the queue ( #390 )"
...
This reverts commit a84a961a39
.
The changes to RegisterCrossing.scala were unneeded after application of this branch.
The name changes made to the AsyncQueue.scala are reapplied at the end of this branch.
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
adf5f1807b
tilelink2: ToAXI4 bridge added
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
e856cbe3a6
axi4: SRAM for testing
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
abb02aa6f4
axi4: add a RegisterRouter for generic devices
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
2f7081aeaf
tilelink2: make mask generation reusable
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
b29d34038e
axi4: diplomacy capable AXI4
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
dcb9383568
PositionalMultiQueue: work around vcs Lint report
...
Lint-[PCTIO-L] Ports coerced to inout
rocket-chip/vsim/generated-src/unittest.UncoreUnitTestConfig.v, 127524
"io_deq_0_valid"
Port "io_deq_0_valid" declared as output in module "PositionalMultiQueue_16"
may need to be inout. Coercing to inout.
2016-10-10 11:21:49 -07:00
Wesley W. Terpstra
5d905a5310
PositionalMultiQueue: shared storage FIFO 1-push n-pop
2016-10-10 11:21:49 -07:00
mwachs5
3a1d8fe482
debug: use a different form of the crossing which doesn't create an AsyncScope ( #394 )
2016-10-09 20:33:18 -07:00
mwachs5
b5d4b72313
register_crossing: Remove the need for AsyncScope by specifying the master clock and reset. ( #393 )
2016-10-09 15:51:23 -07:00
Henry Cook
1e69a2dc1c
[tilelink2] allow TL monitors to be globally enabled or disabled ( #392 )
2016-10-09 12:34:10 -07:00
Andrew Waterman
53360f4c2c
Disable U-mode by default unless S-mode is present
2016-10-08 21:29:40 -07:00
Andrew Waterman
7f429e8799
Simplify AsyncResetReg
...
No need for AsyncSetReg, as AsyncResetReg can be used exclusively with
inverted inputs.
2016-10-08 21:29:40 -07:00
mwachs5
a84a961a39
async_queue: Give names to all the registers which show up in the queue ( #390 )
...
This is to aid debugging but even more so for backend constraint writers, who generally
need predictable names for registers to set false paths, etc.
2016-10-08 17:50:50 -07:00
Andrew Waterman
4fd03ffdf1
Fix PopCountAtLeast, un-breaking BTB
2016-10-07 21:20:40 -07:00
Wesley W. Terpstra
e5ac0f717f
tilelink2: split isolation gates by direction
2016-10-07 12:03:43 -07:00
Albert Ou
ad618fd55d
plic: Fix bit extraction
2016-10-06 18:05:03 -07:00
Andrew Waterman
b1c777c7a2
Fix PLIC enable bit access for #ints >= tlDataBits
2016-10-06 16:21:14 -07:00
Andrew Waterman
c22438b822
Fix an overly strict D$ assertion
2016-10-06 15:52:46 -07:00
Jacob Chang
fe641c14a1
tilelink2: Add support for different noise generator in fuzzer ( #386 )
2016-10-06 13:20:13 -07:00
Andrew Waterman
5980dc160f
Don't allow multiple entries for same PC in BTB
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Necessary for RVC forward-progress guarantee.
2016-10-06 11:30:45 -07:00
Andrew Waterman
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
Andrew Waterman
67593fdf2d
Explicitly zap some S-mode CSRs when not using S-mode
2016-10-04 22:29:39 -07:00
Andrew Waterman
968851f7e3
Default to configurable priorities
...
up-to-7 levels is kind of arbitrary, but I'm unwilling to introduce
a new Parameter at the moment.
2016-10-04 22:29:39 -07:00
mwachs5
e952f8f222
asyncqueue: Fix typo in the Async Queue ( #381 )
...
* asyncqueue: Fix typo in the Async Queue that would cause the sync depth to be one less than expected.
* asyncqueue: Typo in the typo fix
2016-10-04 21:02:06 -07:00
Andrew Waterman
064c9ebdc6
Don't report I$ fetch faults on TLB misses!
2016-10-04 14:37:25 -07:00
Andrew Waterman
516481b68b
Improve back-to-back integer multiplication performance
...
More exact hazard checking in the decode stage avoids a pipeline flush.
2016-10-04 14:37:25 -07:00
Andrew Waterman
7b69f1f261
Don't enter D$ flush state machine if grant outstanding
2016-10-04 14:37:25 -07:00
Andrew Waterman
28beb33943
Make any intervening load/store/fence fail an LR/SC sequence
...
This catches LR/SC misuses more quickly.
2016-10-04 14:37:25 -07:00
Yunsup Lee
62954d543e
correctly initialize the active flag
2016-10-03 17:56:30 -07:00
Wesley W. Terpstra
6ec2e7c5bd
tilelink2: Legacy should preserve the access size ( #378 )
...
* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
2016-10-03 17:25:31 -07:00
Wesley W. Terpstra
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
c85e42a303
tilelink2: Nodes should accept full PortParameters
...
We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
2016-10-03 16:09:49 -07:00
Wesley W. Terpstra
f2ca2178bf
graphML: CTO's like colour
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
fe0875b084
LazyModule: output final verilog Module name
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
0a4ef66894
BaseTop: record top module; more general than GraphML
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
52c1a053ff
tilelink2 RegisterRouter: test fully Decoupled behaviour
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
422e6357a4
tilelink2 RegisterCrossing: Queues go from RV to Irrevocable
...
AsyncQueue is still a Queue.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
02f89fb530
RegMapper: clarify interface is DecoupledIO
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
8a268268ad
tilelink2 RegField: clarify restrictions on functions
...
RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
bff0ffa428
tilelink2 RegisterRouter: fix output data glitches
...
If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
2016-10-02 02:24:02 -07:00
Andrew Waterman
e0188f8aa4
Don't implicitly fence on CSR instructions
...
CSRs that have an effect on I/O should use an explicit FENCE.
2016-10-01 19:44:10 -07:00
Andrew Waterman
b772edcb1b
Allow hit-under-MMIO and multiple MMIOs in blocking D$
...
The latter feature is by default disabled, since there aren't enough
ID bits.
2016-10-01 19:44:05 -07:00
Megan Wachs
28eba9b5ac
clint/plic: Move the default addresses
2016-10-01 15:46:55 -07:00
mwachs5
9a381e88d1
Suggest sane names for common objects ( #369 )
...
* Suggest sane names for common objects frequently instantiated with factory methods
* Suggest names for common primitives using more Scala-esque Options
2016-09-30 16:19:25 -07:00
Wesley W. Terpstra
0ebab0976a
tilelink2 Isolation: add enable signal ( #368 )
2016-09-30 04:54:40 -07:00
Wesley W. Terpstra
d3547a6193
tilelink2: Isolation gate insertion module
2016-09-30 01:50:33 -07:00
Wesley W. Terpstra
9b0654be52
tilelink2 Crossing: helpful constructor objects
2016-09-30 01:48:47 -07:00
Wesley W. Terpstra
80f7bb49e3
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Howard Mao
4b86802b1a
change the configuration interface of SlowIO
2016-09-29 22:16:53 -07:00
Wesley W. Terpstra
6d8c965f04
tilelink2 Crossing: cut the crossing between clock domains
2016-09-29 17:35:10 -07:00
Wesley W. Terpstra
20f42a8762
tilelink2: reuse the halves of the AsyncQueue
2016-09-29 17:35:08 -07:00
Wesley W. Terpstra
8e4c1e567c
tilelink2: add types for a TL clockless interface
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
02ce8c2ca4
tilelink2 Nodes: rename RootNode => BaseNode
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
754fcf9831
tilelink2: rename BaseNode to SimpleNode
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
cfdb8ca797
tilelink2 LazyModule: remove obsolete connect method
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
f2e438833c
tilelink2 Nodes: generalize a node into inner and outer halves
...
This lets us create nodes which transform from one bus to another.
2016-09-29 17:33:11 -07:00
Andrew Waterman
2bdf8c2be7
Merge branch 'master' into move-to-util
2016-09-29 14:42:11 -07:00
Howard Mao
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Andrew Waterman
e928b741ce
Default mtvec=0, not None
...
Setting it to None was a mistake. It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.
2016-09-29 13:52:41 -07:00
Megan Wachs
45bd63fcc6
jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec
2016-09-29 13:49:14 -07:00
Megan Wachs
449d689a4e
jtag: Connect the JTAG DTM side of the synchronizer!
2016-09-29 13:48:55 -07:00
Yunsup Lee
0924f8adb0
print out assigned inerrupt ranges
2016-09-29 11:59:32 -07:00
Yunsup Lee
4c3e8ec1b4
assign interrupt ranges deterministically
2016-09-29 11:59:32 -07:00
Henry Cook
7bca99a27a
[tilelink2] Add unit test configs to regression
2016-09-28 18:02:04 -07:00
Henry Cook
32f3f94882
[tilelink2] Fix zero-width wires in RAMModel.
2016-09-28 18:02:04 -07:00