Henry Cook
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c6f252a913
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Remove Option from success flag in coreplex; just use a sane default.
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2016-09-15 12:19:22 -07:00 |
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Henry Cook
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9e2b0aad65
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Revert "allow MODEL to be something other than TestHarness"
This reverts commit bf253aaa97.
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2016-09-15 11:53:05 -07:00 |
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Henry Cook
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888f6a2a55
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Revert "move UnitTest back into rocketchip module"
This reverts commit f95b8c4ec2.
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2016-09-15 11:48:09 -07:00 |
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Henry Cook
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29ce599ea2
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Merge pull request #295 from ucb-bar/tl2-irrevocable
TL2 -> IrrevocableIO
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2016-09-15 11:33:05 -07:00 |
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Henry Cook
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0a65238920
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Merge branch 'master' into tl2-irrevocable
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2016-09-15 10:30:50 -07:00 |
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Howard Mao
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49863944c4
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merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer
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2016-09-14 21:36:27 -07:00 |
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Howard Mao
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f363f5f709
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wrap TestHarness latency pipe in module
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2016-09-14 21:16:54 -07:00 |
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Howard Mao
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f5db83a72f
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NTiles should not be a Knob
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2016-09-14 21:16:54 -07:00 |
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Howard Mao
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646527c88e
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use named constants to set AXI resp, cache, and prot fields
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2016-09-14 21:16:54 -07:00 |
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Howard Mao
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f95b8c4ec2
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move UnitTest back into rocketchip module
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2016-09-14 20:51:56 -07:00 |
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Howard Mao
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bf253aaa97
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allow MODEL to be something other than TestHarness
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2016-09-14 20:51:56 -07:00 |
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Howard Mao
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8550582f84
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remove redundant verilator rule
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2016-09-14 20:31:17 -07:00 |
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jackkoenig
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a304695ffd
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Add firrtl and verilog Makefile targets to vsim
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2016-09-14 20:29:59 -07:00 |
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Henry Cook
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cde104b3fa
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[junctions] Removes the obsoleted SMI.
Closes #280.
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2016-09-14 20:06:22 -07:00 |
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Yunsup Lee
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96110caca1
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Merge pull request #291 from ucb-bar/move-bootrom
Move BootROM from Coreplex to Periphery
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2016-09-14 19:51:16 -07:00 |
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Henry Cook
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ab3814dcee
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Merge branch 'master' into tl2-irrevocable
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2016-09-14 19:00:17 -07:00 |
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Yunsup Lee
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e404bea2ee
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Merge branch 'master' into move-bootrom
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2016-09-14 18:58:48 -07:00 |
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Yunsup Lee
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f2cb9da91a
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Merge pull request #296 from ucb-bar/split-unittest
refactor unittest framework
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2016-09-14 18:56:11 -07:00 |
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Wesley W. Terpstra
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1c7d7f9d32
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tilelink2 RegisterRouterTest: stall on both edges
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2016-09-14 18:22:12 -07:00 |
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Yunsup Lee
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97809b183f
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refactor unittest framework
as a result, there's another SUITE that needs to run
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2016-09-14 18:10:21 -07:00 |
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Henry Cook
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d35060b881
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[junctions] messed up the merge lulz
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2016-09-14 17:55:16 -07:00 |
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Henry Cook
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1b53e477fa
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Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
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2016-09-14 17:50:17 -07:00 |
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Henry Cook
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e02d149cbe
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Henry Cook
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3030718f72
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bump chisel3
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2016-09-14 17:40:22 -07:00 |
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Henry Cook
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08c4c7b985
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[junctions] make async crossings capable of providing IrrevocableIO
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2016-09-14 17:38:54 -07:00 |
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mwachs5
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ae026edeb3
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Merge pull request #293 from ucb-bar/async_clk_utils
Add some async/clock utilities
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2016-09-14 16:59:27 -07:00 |
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Megan Wachs
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1308680f75
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Add some async/clock utilities
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2016-09-14 16:30:59 -07:00 |
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Yunsup Lee
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710f1ec020
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Move BootROM from Coreplex to Periphery
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2016-09-14 16:09:59 -07:00 |
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Henry Cook
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aa3fa90fe3
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[tilelink2] Monitor: miscopied name in assert message
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2016-09-14 14:56:50 -07:00 |
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Henry Cook
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d76e19a6ab
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[tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both?
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2016-09-14 14:23:23 -07:00 |
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Scott Beamer
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f7121a2a5b
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support for BSD sed (GNU sed still works)
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2016-09-14 12:21:39 -07:00 |
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Scott Beamer
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cd12fd1cbb
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fix clang support for emulator-debug
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2016-09-14 12:20:37 -07:00 |
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Andrew Waterman
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565444c40e
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Make UnitTestCoreplex cope with an external MMIO network
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2016-09-14 12:19:21 -07:00 |
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Andrew Waterman
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2572cd3f7c
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Add missing dependency
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2016-09-14 11:50:28 -07:00 |
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Andrew Waterman
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5828e6042e
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Work around https://github.com/ucb-bar/firrtl/issues/299
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2016-09-14 11:47:10 -07:00 |
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Andrew Waterman
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c3ddff809b
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Move PRCI from Coreplex to always-on block, where it belongs
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2016-09-14 11:01:05 -07:00 |
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Andrew Waterman
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5566bf1b13
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Don't route PLIC interrupts through PRCI
The PLIC is local to the Coreplex, and PRCI should not be.
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2016-09-14 11:01:05 -07:00 |
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Andrew Waterman
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38b13da2f4
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Bump chisel and firrtl
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2016-09-14 11:01:05 -07:00 |
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mwachs5
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47acbf928b
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Give AsyncCrossing slave interfaces registers visibility into when they were written (#288)
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2016-09-14 00:17:26 -07:00 |
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Howard Mao
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bdb7b1de36
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move tilelink-agnostic counters from uncore to util package
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2016-09-13 20:47:05 -07:00 |
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Howard Mao
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1882241493
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move junctions utils into top-level utils package
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2016-09-13 20:47:04 -07:00 |
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Henry Cook
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7dd4492abb
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First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
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2016-09-13 20:30:14 -07:00 |
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Wesley W. Terpstra
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dfd6bfb454
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Merge pull request #287 from ucb-bar/crossing-take-2
Clock crossing redux
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2016-09-13 19:13:21 -07:00 |
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Wesley W. Terpstra
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d23ab7370d
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tilelink2: Unit Test for the RegisterCrossing
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2016-09-13 18:33:56 -07:00 |
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Wesley W. Terpstra
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cc88bf1b08
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junctions: give unit tests more time
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2016-09-13 18:33:56 -07:00 |
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Wesley W. Terpstra
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acedd3688a
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tilelink2: unit test for the clock crossing
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2016-09-13 18:33:56 -07:00 |
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Wesley W. Terpstra
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c8e6d47884
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tilelink2: add a clock crossing adapter
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2016-09-13 18:33:56 -07:00 |
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Wesley W. Terpstra
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44501cdbf8
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crossings: change defaults to sync=3 for safer settling time
Make the matching AsyncQueue depth=8 to support full throughput
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2016-09-13 18:33:56 -07:00 |
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Wesley W. Terpstra
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3348236320
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junctions: remove obsolete Handshaker crossing
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2016-09-13 18:33:56 -07:00 |
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Wesley W. Terpstra
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fe6a67dd0e
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tilelink2: add a RegisterCrossing primitive
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2016-09-13 18:33:53 -07:00 |
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